Semiconductor integrated circuit and delayed clock signal...

Details Semiconductor integrated circuit and delayed clock signal... Semiconductor integrated circuit and delayed clock signal...

2001-05-29

2002-10-22

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S264000, C327S276000, C327S277000, C327S278000, C327S393000, C327S394000

Reexamination Certificate

active

06469557

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for generating a delayed clock signal synchronized with an input clock signal and relates to a circuit for use in the timing control of a sense amplifier of, e.g., an SRAM (Static Random Access Memory).
2. Related Background Art
Since a semiconductor storage device, especially an SRAM, can read/write data at a high speed, it is extensively used for a cache memory and the like. Although data read from a memory cell is supplied to a pair of bit lines, a difference in potential of a pair of bit lines is very small, and the data must be amplified by using a sense amplifier.
Since a latch type sense amplifier which is a one-circuit type of the sense amplifier can read data at a high speed, it is adopted to a high speed memory and the like.
FIG. 1
is a circuit diagram showing the structure of the periphery of a latch type sense amplifier of a conventional SRAM. As shown in the drawing, the sense amplifier includes: PMOS transistors Q
11
and Q
12
and NMOS transistors Q
13
and Q
14
constituting a flip flop; PMOS transistors Q
15
and Q
16
for switching whether or not to apply voltages of bit lines BL and BLB to the flip flop; an NMOS transistor Q
17
for switching whether or not to perform the sense operation by the sense amplifier; and a timing generating circuit
11
for controlling on/off of the NMOS transistor Q
17
.
The timing generation circuit
11
is constituted by a plurality of cascade-connected inverters as a most simplified structure as shown in the drawing. The sense amplifier can be operated with an optimum timing by adjusting the number of stages of the inverters.
Since the latch type sense amplifier performs the sense operation in synchronization with an input clock signal, the timing must be designed so that the latch type sense amplifier can normally operate even if a frequency of the input clock signal is changed.
In case of the circuit shown in
FIG. 1
, however, the time from rising of the input signal to activation of the sense amplifier does not change even if the circuit is operated at a frequency lower than a target operating frequency, and hence there is a problem that a sense margin does not increase.
The sense margin becomes critical when the sense amplifier performs the operation at a high speed. For example, in the circuit illustrated in
FIG. 1
, if the operation timing of the sense amplifier is decided by using the timing at the time of the high speed operation as a reference, the operation timing of the sense amplifier quickens even at the time of the low speed operation. Thus, an erroneous operation may occur at the time of the low speed operation as well as the high speed operation.
On the other hand, although use of a synchronous circuit such as a PLL (Phase Locked Loop) circuit can be considered as a technique for obtaining a timing signal having a fixed phase with respect to a frequency of the input clock signal, the circuit scale becomes large, and the design is also complicated, which may lead to increase in the cost. Therefore, a simpler technique is desirable.
SUMMARY OF THE INVENTION
In view of the above-described problems, it is an object of the present invention to provide a semiconductor integrated circuit and a delayed clock signal generation method capable of simply and rapidly adjusting a delay time of a delayed clock signal in accordance with a change in frequency of an input clock signal.
To achieve this aim, there is provided a semiconductor integrated circuit for generating based on an input clock signal a delayed clock signal synchronized with the input clock signal, comprising:
an edge pulse generating circuit configured to generate a control pulse signal at a first cycle of the input clock signal based only on a leading edge or a trailing edge of the input clock signal; and
a delay time setting circuit configured to set a delay time of the delayed clock signal in a second cycle of the input clock signal after the first cycle based on the control pulse signal.
According to the present invention, since a delay time of the delayed clock signal in a second cycle corresponding to the control pulse signal is set based on the control pulse signal generated by using a leading edge or a trailing edge of the input clock signal as a reference, the delay time of the delayed clock signal can be simply and rapidly adjusted in accordance with a change in frequency of the input clock signal. Therefore, when the control for switching the sense operation of the sense amplifier is conducted by using the delayed clock signal, it is possible to perform the sense operation of the sense amplifier with a timing optimum for a frequency of the input clock signal.
Furthermore, a semiconductor integrated circuit configured to generate a delay clock signal synchronized with an input clock signal based on the input clock signal, comprising:
a control pulse generating circuit configured to generate a control pulse signal of the input clock signal based on a leading edge or a trailing edge of the input clock signal; and
a delay time setting circuit configured to set a delay time of the delay clock signal based on the control pulse signal, the delay time setting circuit comprising:
first to nth delaying circuits connected in series, each of the first to nth delaying circuits propagating the input clock signal in order;
(n+1)st to 2nth delaying circuits connected in series, each of the (n+1)st to 2n circuits propagating the control pulse signal, and the (n+1)st to 2nth delaying circuits corresponding to the first to nth delaying circuits, respectively,
wherein the delay time in each of the first to nth delaying circuits is set based on the control pulse signal and output of the corresponding one of the 2nth to (n+1)st delaying circuits.


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