Semiconductor integrated circuit and data processing system

Details Semiconductor integrated circuit and data processing system Semiconductor integrated circuit and data processing system

1999-06-29

2002-04-30

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S003000, C711S100000, C711S118000

Reexamination Certificate

active

06381671

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit in which memories are integrated. Particularly, it relates to a semiconductor integrated circuit in which a logic circuit such as a CPU (central processing unit) is integrated with a large-capacity memory in one chip. For example, it relates to a useful technique adapted for embedded DRAM which is integrated with a CPU and a first level cache memory in one and the same chip.
Today, a semiconductor integrated circuit in which a large-scale logic circuit is integrated with a large-capacity memory in one chip is provided. In such a semiconductor integrated circuit, the number of bus bits for connecting the memory and the logic circuit to each other can be increased easily, for example, to 128 in order to enhance data throughput between the memory and the logic circuit. Accordingly, there is an advantage in that data can be transferred at a high speed while electric power consumption required for data input/output is suppressed compared with the case where input/output pins outside the chip are driven.
Multi-bank DRAM (Dynamic Random Access Memory) can be used as the large-capacity memory. In the multi-bank DRAM, a sense amplifier is provided in accordance with every memory bank, so that data once latched by the sense amplifier on the basis of a word line selecting operation can be output successively at a high speed by a simple means for changing-over a column switch. Accordingly, data access to continuous addresses in one and the same page (one and the same word line address) can be made relatively speedily. Data access to different pages (at page-miss) is, however, made slow because of bit line precharge, or the like.
Further, in the multi-bank DRAM, page-miss can be hidden under a predetermined condition. That is, when a read or write command is generated to operate a certain memory bank and another memory bank is to be used next, an activation command can be given to the next memory bank in advance to make a word line selecting operation precedently. Of course, for this reason, the CPU must make access to the addresses sequentially. It is, however, substantially impossible to define this entirely by a CPU operation program, or the like.
In semiconductor integrated circuits, there is also that in which a cache memory integrated with a large-capacity memory and a large-scale logic circuit such as a CPU, or the like. In the semiconductor integrated circuit of this type, the difference in operating speed between the large-capacity memory and the CPU is relaxed by the cache memory so that data can be processed at a high speed by the CPU. That is, among data stored in the large-capacity memory, a part of data used recently by the CPU and data in its vicinity are held in the high-speed cache memory. The data processing speed is enhanced when the memory access of the CPU is hit to the cache memory. However, when a miss occurs once, access to the large-capacity memory is made. As a result, data processing speed of the CPU is limited.
An example of literature on the multi-bank DRAM is JP-A-10-65124 corresponding to U.S. patent application Ser. No. 08/813900 filed Mar. 7, 1997 and U.S. patent application Ser. No. 09/188367 filed Nov. 10, 1998, a continuation application of application Ser. No. 08/813900, the whole disclosure of which is incorporated herein by reference.
As described above, even in the multi-bank DRAM, page-miss is not always hidden in accordance with a sequence of access addresses. Even in the case where a cache memory is provided for the multi-bank DRAM, the situation is quite the same if cache-miss occurs. Therefore, the necessity of improving the access speed to the multi-bank memory more greatly has been found by the inventor.
SUMMARY OF THE INVENTION
A first object of the present invention is to enhance the speed of first access to a multi-bank memory, that is, the speed of read access different in word line from the previous access.
A second object of the present invention is to prevent lowering of the operating efficiency of a multi-bank memory having a plurality of banks which are able to operate parallelly when both cache entry replace and write back are caused by cache-miss of a cache memory provided for the multi-bank memory. That is, address information corresponding to an index address in an address signal is made identical between an operation in which data in a cache line to be written back are written in a multi-bank memory and an operation in which new cache entry data to be written in the same cache line as described above are read from the multi-bank memory. When information of the index address is mapped in memory bank selection address information, data having the index addresses arranged as one and the same address are arranged in one and the same memory bank. Accordingly, both a read operation for replacing the cache line with new one and a write operation for write back must be performed on one and the same memory bank. Accordingly, the two operations cannot be performed efficiently by use of different memory banks.
A third object of the present invention is to make non-blocking multi-access possible in a semiconductor integrated circuit having a plurality of multi-bank memory macro structures in which a plurality of access requests without conflict among the memory macro structures are allowed so that one access does not block another access.
A fourth object of the present invention is to enhance the efficiency of data rewrite to a multi-bank DRAM having a cache line with every word line. That is, the inventor has found that, when the cache line is provided as a rewrite unit, there is no necessity of performing read modify write to apply write data after storage information read out to a bit line by a word line selecting operation is latched by a sense amplifier, in the same manner as in a general DRAM.
The foregoing and other objects and novel features of the present invention will become clear from the following description and the accompanying drawings.
Main features in embodiments of the present invention contain the following features.
<1> Next Address Self-Prefetching
A multi-bank memory macro structure is used and data are held in a sense amplifier in every memory bank. When access is hit to the data held in the sense amplifier, data latched by the sense amplifier are output so that the speed of first access to the memory macro structure can be made high. That is, every memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of the sense amplifier cache (the ratio of hit on the data of the sense amplifier) more greatly, after access to one memory bank, the next address (obtained by addition of a predetermined offset) is self-prefetched so that data in the self-prefetching address is preread by a sense amplifier in another memory bank. The next address is used as a subject of self-prefetching on the basis of an empirical rule that CPU operation programs or a group of processing data are basically mapped on linear addresses.
A semiconductor integrated circuit for achieving the aforementioned next address self-prefetching comprises memory macro structures
5
M
a
to
5
M
d
, and an access controller
4
. Each of the memory macro structures has a plurality of memory banks BANK
1
to BANK
4
having bank addresses allocated thereto respectively. Each of the memory banks has a sense amplifier
53
for latching storage information read out to a bit line BL from a memory cell in a word line WL selected on the basis of a row address signal R-ADD. The bit line is selected on the basis of a column address signal Ys
0
to Ys
7
. The selected bit line is connected to a data line GBL of the memory macro structure. The access controller includes an address/command generating unit
44
for generating the address/command and being able to operate for every memory bank, a hit/miss judgment unit
43
for enabling data already latched by the sense amplifier to be output to the data line in response to an access request after the

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