Semiconductor integrated circuit and circuit designating system

Details Semiconductor integrated circuit and circuit designating system Semiconductor integrated circuit and circuit designating system

2005-03-08

2005-03-08

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S295000

Reexamination Certificate

active

06864720

ABSTRACT:
A semiconductor integrated circuit is disclosed, which comprises a tree structure of buffer circuit groups configured to have an enable-signal-controlled AND buffer circuit at least in a final stage, a latch circuit provided in a correspondence to the enable-signal-controlled AND buffer circuit and configured to receive an enable signal and clock signal and deliver an output to an input portion of a final stage buffer circuit, an enable-signal-controlled AND buffer circuit provided in a portion of an intermediate stage of the buffer circuit groups, and an OR circuit provided in a correspondence to the intermediate stage enable-signal-controlled AND buffer circuit and configured to take a logical sum of a plurality of enable signals for controlling the operations of a plurality of enable-signal-controlled AND buffer circuits more on a load circuit side and deliver a logical sum output to an input portion of the intermediate stage enable-signal-controlled AND buffer circuit.

REFERENCES:
patent: 5892373 (1999-04-01), Tupuri et al.
patent: 5923188 (1999-07-01), Kametani et al.
patent: 6020774 (2000-02-01), Chiu et al.
patent: 6246277 (2001-06-01), Nitta et al.
patent: 2001-84287 (2001-03-01), None
patent: 2001-155045 (2001-06-01), None

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