Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-08-04
2000-12-05
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714733, 365201, G11C 2900, G01R 3128
Patent
active
061580287
ABSTRACT:
At a test of built-in memory of a conventional semiconductor integrated circuit, data is written into the memory one address by one address and confirmed the data one by one, in case of mass memory many test patterns and many test time are required. The present invention comprises a memory which is capable of data writing and reading. Also including is a device for setting the memory in the test state, a device for setting a predetermined length of arbitrary data written into the memory, and a device for writing in a batch process into the memory in a form of filling the memory area of the memory with the arbitrary data.
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Moise Emmanuel L.
NEC Corporation
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