Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2009-08-12

2010-10-19

Cho, James (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S014000, C326S046000, C327S202000

Reexamination Certificate

active

07816950

ABSTRACT:
Semiconductor integrated circuit has a control circuit. The control circuit causes the clock signal generating circuit to control the first clock signal and the second clock signal to make a logic of data held by the first data holding terminal and a logic of data held by the second data holding terminal equal to each other, and switches on the switch circuit, and the error detection circuit senses a logic of the first data holding terminal and a logic of the second data holding terminal after switching on the switching circuit.

REFERENCES:
patent: 6788105 (2004-09-01), Kono
patent: 7167024 (2007-01-01), Momtaz et al.
patent: 7409631 (2008-08-01), Tschanz et al.
Yoshihide Komatsu, et al., “A Soft-Error Hardened Latch Scheme for SoC in a 90nm Technology and Beyond”, IEEE 2004 Custom Integrated Circuits Conference, 2004, pp. 329-332.
Yoichi Sasaki, et al., “Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit”, Proceedings of the 21stIEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006, 9 pages.
T. Calin, et al., “Upset Hardened Memory Design for Submicron CMOS Technology”, IEEE Transactions on Nuclear Science, vol. 43, No. 6, Dec. 1996, 5 pages.
Ashish Góel, et al., “Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability”, Digest of Technical Papers, Asia and South Pacific Conference on Design Automation, 2006, pp. 665-670.

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