Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1998-05-22

2000-09-12

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

365201, G11C 2900

Patent

active

061192503

ABSTRACT:
A test-target circuit is constructed of circuit blocks each comprising low-Vth MOS transistors including address buffers and a timing generator. A test enable signal for indication of a test, an operation selection signal for indication of an operation, and a block selection signal used to select a desired circuit block are provided. A high-Vth NMOS and a high-Vth PMOS transistor are provided in order to provide to a test circuit one of detected currents of the circuit blocks that was selected by placing a block selection signal and the test enable signal in the state of HIGH.

REFERENCES:
patent: 5636163 (1997-06-01), Furutanu et al.
Y. Matsuya, et al., "1V, 10MHz High-Speed Digital Circuit Technology with Multi-Threshold CMOS", Technical Report of IEICE, ICD93-107, pp. 23-27, 1993-10.
C.Q. Tong, et al., "IDDQ Testing in Low Power Supply CMOS Circuits", Proc. of IEEE 1996 Custom Integrated Circuits Conference, pp. 467-470, 1996.
T. Kuroda, "A High-Speed Low Power 0.3 .mu.m CMOS Gate Array with Variable Threshold Voltage (VT) Scheme", Proc. of IEEE 1996 Custom Integrated Circuits Conference, pp. 53-56, 1996.
T. Kuroda, et al., A 0.9V 150 HMz 10mW 4mm.sup.2 2-D discrete Cosine Transform Core Processor with Variable-Threshold-voltage Scheme, Proc. of 1996 IEEE International Sold-State Circuits Conference, pp. 166-167, 1996.

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