Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
Reexamination Certificate
2008-03-13
2010-12-14
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Skew detection correction
C714S744000
Reexamination Certificate
active
07853836
ABSTRACT:
A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data.
REFERENCES:
patent: 5793822 (1998-08-01), Anderson et al.
patent: 7142623 (2006-11-01), Sorna
patent: 7558991 (2009-07-01), Mattes et al.
patent: 2007/0113119 (2007-05-01), Hafed et al.
patent: 2009/0086801 (2009-04-01), Liu et al.
patent: 2006-025114 (2006-01-01), None
Kabushiki Kaisha Toshiba
Kerveros James C
Turocy & Watson LLP
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