Semiconductor integrated circuit

Static information storage and retrieval – Addressing – Multiple port access

Reexamination Certificate

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C365S154000

Reexamination Certificate

active

07630273

ABSTRACT:
During a write cycle, a selected write-word-line driver drives the corresponding write word line such that the potential of the corresponding write word line is lower in a first period as a predetermined period after an initiation of the write cycle than in a second period as a predetermined period after the first period, and sense amplifiers amplify the potentials of the corresponding write bit lines in the first period.

REFERENCES:
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patent: 6201758 (2001-03-01), Morishima et al.
patent: 6483754 (2002-11-01), Agrawal
patent: 6967861 (2005-11-01), Braceras et al.
patent: 7113421 (2006-09-01), Maeda et al.
patent: 7289354 (2007-10-01), Houston
Morita, Yasuhiro et al., “An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 256-257, 2007.

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