Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2007-07-17
2009-10-27
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S401000, C713S500000
Reexamination Certificate
active
07610504
ABSTRACT:
A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network. The semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value which is different from a value of the first power supply voltage.
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Ian A. Young, et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
Kabushiki Kaisha Toshiba
Lee Thomas
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Rehman Mohammed H
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