Semiconductor integrated circuit

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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Reexamination Certificate

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07447059

ABSTRACT:
A semiconductor integrated circuit having an internal SRAM that includes a plurality of arrayed memory cells, including a first bit line and a second bit line that are connected to first ports and a third bit line and a fourth bit line that are connected to second ports of the memory cells, a first and second transistor respectively compose first ports of adjacent first and second memory cells and having shared impurity diffusion region connected to the first bit line via a first interconnection, a third transistor composing a second port of the first memory cell and having an impurity diffusion region connected to the third bit line via a second interconnection a fourth and fifth transistor respectively composing the first ports of the first and second memory ceils and having a shared impurity diffusion region connected to the second bit line via a third interconnection.

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patent: 4922459 (1990-05-01), Hidaka
patent: 5500814 (1996-03-01), Kinoshita et al.
patent: 2004/0218455 (2004-11-01), Nii
patent: 2005/0047256 (2005-03-01), Yang
patent: 2005/0253267 (2005-11-01), Takao
patent: 10-222983 (1998-08-01), None
patent: 2003-078036 (2003-03-01), None
patent: 2003-085976 (2003-03-01), None

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