Semiconductor integrated circuit

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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Details

C257S207000

Reexamination Certificate

active

07459934

ABSTRACT:
A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

REFERENCES:
patent: 6239614 (2001-05-01), Morikawa
patent: 6433584 (2002-08-01), Hatae
patent: 6989686 (2006-01-01), Arakawa
patent: 06-206420 (1993-06-01), None
patent: 07-245347 (1995-09-01), None
patent: 2001-298090 (2001-10-01), None
patent: 2003-158189 (2003-05-01), None

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