Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-04-29
2008-04-29
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
10892298
ABSTRACT:
Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in the updating of X addresses, Y addresses, and bank addresses. A variety of addressing modes provided expand BIST-based test functions.
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Takamine Yoshio
Yamasaki Kaname
Louis-Jacques Jacques
Renesas Technology Corp.
Tabone, Jr. John J.
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