Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-01-02
2007-01-02
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C327S295000, C331S049000
Reexamination Certificate
active
11008957
ABSTRACT:
A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.
REFERENCES:
patent: 5596302 (1997-01-01), Mastrocola et al.
patent: 5777567 (1998-07-01), Murata et al.
patent: 59-63822 (1984-04-01), None
patent: 06-152347 (1994-05-01), None
patent: 11-150446 (1999-06-01), None
Dinh Son T.
Sughrue & Mion, PLLC
Thine Electronics Inc.
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