Semiconductor integrated circuit

Static information storage and retrieval – Addressing – Multiple port access

Reexamination Certificate

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C365S149000, C365S189011

Reexamination Certificate

active

07139214

ABSTRACT:
An apparatus and method to reduce, during standby time, electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.

REFERENCES:
patent: 5831896 (1998-11-01), Lattimore et al.
patent: 5995433 (1999-11-01), Liao
patent: 6452834 (2002-09-01), Kengeri
patent: 6576943 (2003-06-01), Ishii et al.
patent: 6787835 (2004-09-01), Atwood et al.
patent: 6903962 (2005-06-01), Nii
patent: 2000-011642 (2000-01-01), None

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