Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-08-15
2006-08-15
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000
Reexamination Certificate
active
07092313
ABSTRACT:
A semiconductor integrated circuit disclosed herein, comprises a first core which realizes a predetermined function; a second core which is different from the first core and realizes a predetermined function; a power supply circuit which is capable of supplying, to the first core, a power supply voltage different from that supplied to the second core; and a clock generating circuit which supplies a clock signal to each of the first core and the second core, the clock generating circuit including a clock skew reducing circuit which reduces clock skew occurring between the clock signal in the first core and the clock signal in the second core.
REFERENCES:
patent: 5726950 (1998-03-01), Okamoto et al.
patent: 6091663 (2000-07-01), Kim et al.
patent: 6111448 (2000-08-01), Shibayama
patent: 6525587 (2003-02-01), Makino
patent: 6791370 (2004-09-01), Morzano
patent: 6930953 (2005-08-01), Heragu et al.
Terazawa Toshihiro
Watanabe Yoshinori
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