Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2005-08-09

2005-08-09

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000, C711S105000

Reexamination Certificate

active

06928594

ABSTRACT:
A logic in DRAM LSI is disclosed, which comprises a plurality of DRAM circuits, a control circuit that receives a test control signal to perform a test control in which the plurality of RAM circuits are tested while the access to the plurality of DRAM circuits is subsequently changed for each row, an input selector that is controlled by the control circuit and inputs a DRAM macro signal to the plurality of DRAM circuits at the time of a test, and an output selector that is controlled by the control circuit, and outputs output signals of the plurality of DRAM circuits sequentially to a macro output terminal at the time of the test. According to the DRAM integrated LSI, a test time required to test the plurality of DRAM circuits integrated in the LSI is shortened. Moreover, data that is read from the plurality of DRAM circuits is transferred in a high speed.

REFERENCES:
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patent: 5913928 (1999-06-01), Morzano
patent: 6072737 (2000-06-01), Morgan et al.
patent: 6163863 (2000-12-01), Schicht
patent: 6169695 (2001-01-01), Duesman
patent: 6216240 (2001-04-01), Won et al.
patent: 7-260884 (1995-10-01), None
patent: 353178 (1999-02-01), None

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