Semiconductor integrated circuit

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S112000, C326S119000, C326S031000

Reexamination Certificate

active

06937068

ABSTRACT:
An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well2and the p-type well3from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well2and the p-type well3to the voltages Vdd and Vss, respectively.

REFERENCES:
patent: 4873668 (1989-10-01), Winnerl et al.
patent: 5461338 (1995-10-01), Hirayama et al.
patent: 5557231 (1996-09-01), Yamaguchi et al.
patent: 5610533 (1997-03-01), Arimoto et al.
patent: 5793691 (1998-08-01), Mullarkey
patent: 6232793 (2001-05-01), Arimoto et al.
patent: 63-090847 (1988-04-01), None
patent: 06-085200 (1994-03-01), None
patent: 06-120439 (1994-04-01), None
patent: 06-334010 (1994-12-01), None
patent: 07-235608 (1995-09-01), None
patent: 08-017183 (1998-01-01), None
English Language Abstract [corresponding to JP 61-20439], published Apr. 28, 1994, Inventor: Takagi Noriaki, Applicant: NEC Corp.,.
W. Maly, “Chapter 5: CMOS Technology,” Zusetsu Cho Eruesuai Kogaku (Illustrated ULSI Engineering) in English, pp. 167-191 (in Japanese with English translation).
T. Kuroda et al., “Low Power Communication Signal Processing,” IEEE International Solid State Circuits Conference, Paper Nos. FA 10.2 and FA 10.3, pp. 166, 167 and 437, (1996).
T. Kuroda et al., “A High-Speed Low Power 0.3 μm CMOS Gate Array with Variable Threshold Voltage (VT) Scheme,” IEEE Custom Integrated Circuits Conference, pp. 53-56, (1996).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3463236

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.