Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop
Reexamination Certificate
2001-08-20
2004-09-07
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Sequential or with flip-flop
C326S016000, C327S202000, C714S726000
Reexamination Certificate
active
06788105
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and in particular, to a semiconductor integrated circuit mounting a logic circuit including a storage element.
In order to detect the stuck-at fault and the like with respect to the logic circuit, the method of scanning a logic circuit is widely used. This method provides the advantage in which the fault can be efficiently detected. Because, when this method is used, it becomes possible to directly manipulate the value of the flipflop (hereinafter, referred to as “FF”) within the logic circuit.
The process of detecting (hereinafter, referred to as “testing”) the fault with respect to the scanned logic circuit will be explained with reference to the drawings.
FIG. 22
is the circuit configuration diagram showing the scan FF used in the conventional technique. This is an example of the multiplexer-type scan FF (hereinafter, referred to as “MUX-type scan FF”). In this configuration, a multiplexer (hereinafter, referred to as “MUX”) g
2602
is connected to an input terminal D of a FF g
2601
. A signal (hereinafter, referred to as “input signal from logic circuit” or “logic input signal”) for performing a normal operation at a front stage is applied through a logic input signal line to the MUX g
2602
from a group of logic gates (hereinafter, referred to as “user logic circuit”). Furthermore, a signal for the scan (hereinafter, referred to as “scan-in signal”) from a FF at the front stage is input through a scan-in signal line. Furthermore, a signal (hereinafter, referred to as “scan-enable signal”) for controlling to change over which the FF g
2601
fetches the logic input signal or the scan-in signal is input through a scan-enable signal line. A logic output signal line for propagating a signal (hereinafter, referred to as “output signal to logic circuit” or “logic output signal”) which is input to a user logic circuit at the rear stage, and a scan-out signal line for propagating a signal for scan (hereinafter, referred to as “scan-out signal”) which is input to a FF at the rear stage are branched in the fork-shape and are connected to an output terminal Q of the FF g
2601
.
FIG. 23
is a diagram showing a logic circuit scanned by the conventional technique. This is an example of the scanned logic circuit formed by connecting the MUX-type scan FFs in multi-stages. In this configuration, the scan-out signal lines of the MUX-type scan FFs g
2701
and g
2702
are respectively connected to the scan-in signal lines of the MUX-type scan FFs g
2702
and g
2703
to form the signal paths of logic circuit (hereinafter, referred to as “paths”). Hereinafter, these paths are referred to as “scan paths”. Also, the scan-in signal line of the MUX-type scan FF g
2701
is connected to the terminal (scan-in terminal) which receives the scan-in signal from the outside of the semiconductor integrated circuit chip (hereinafter, referred to as “chip”). The scan-out signal line of the MUX-type scan FF g
2703
is connected to the terminal (scan-out terminal) which outputs the scan-out signal to the outside of the chip.
The test using the scan FF is conducted by sequentially repeating the following operations.
(1) An operation for substituting the initial values for test into the respective FFs within the logic circuit (hereinafter, referred to as “scan-in operation”);
(2) An operation for inputting the initial values into the user logic circuits from the respective FFs to fetch into the respective FFs the test result values which are output from the user logic circuits (hereinafter, referred to as “logic test operation”); and
(3) An operation for collecting the test result values from the respective FFs (hereinafter, referred to as “scan-out operation”).
The reference numerals a
2704
, a
2705
and a
2706
denote the signal flow at scan-in operation, the signal flow at logic test operation and the signal flow at scan-out operation, respectively.
FIG. 24
is a timing chart showing the operation of the scan FF g
2603
used in the conventional technique. First, at scan-in operation, the scan-enable signal is set to “High” so that the respective FFs can fetch the scan-in signal. In order to substitute the initial values for test into the respective FFs, the clock signal is made to transit (s
2801
) a plurality of times to carry out the shift operation through the scan path. Next, at logic test operation, the scan-enable signal is set to “Low” (s
2802
) so that the respective FFs can fetch the logic output signals. In order to input the initial values for test into the user logic circuits, the clock signal is made to transit one time, and in order to fetch the test result values into the respective FFs, the clock signal is made to transit one time (s
2803
). Moreover, at scan-out operation, in order that the respective FFs can output the scan-out signals, the scan-enable signal is set again to “High” (s
2804
). In order to collect the test result values from the respective FFs, the shift operation similar to the scan-in operation is performed.
However, at scan-in and scan-out operations (hereinafter, referred to as “scan-mode operation” altogether), there is a trend that the probability of operating a logic circuit is usually increased as compared with at user-mode operation. For this reason, the fault detection mistakes due to the excessive voltage drops and the fear of the chip destruction due to the heat generation have been pointed out as the devices become finer, as described in IEEE Computer, vol.32, no.11, p.61, 1999, for example.
In order to avoid this problem, heretofore, it is considered to suppress the power consumption by reducing the frequency at scan-mode operation, as described in DESIGN FOR AT-SPEED TEST, DIAGNOSIS AND MEASUREMENT, Kluwer Academic Publishers, p. 24, 1999, for example. According to this conventional technique, as shown in
FIG. 24
, the frequency of the system clock signal at logic test operation (s
2803
) is made to be the frequency at normal operation of the user logic circuit. Whereas, the frequency of the system clock signal at scan-mode operation (s
2801
) is lowered to reduce the power consumption due to the operation of the user logic circuit at scan-in operation. However, in this method, the time required for the test (test time) becomes long, so that the advantage due to scan will be deteriorated. This is because that the time required for the scan-mode operation normally occupies the most part of the whole test time. As a result, the cost required for the test (hereinafter, referred to as “test cost”) will be increased.
Furthermore, it is considered to reduce the power consumption at scan-mode operation by adding a FF, which is dedicated for the scan-mode operation, within the chip, as described in Digest of Papers 1978 Semiconductor Test Conference, pp. 152-158, for example. However, in this method, the area of the chip will be increased to a great extent. In this respect, according to our inventors' study, it is found that the chip area increases by about 50% as compared with the normal condition.
As mentioned above, in the conventional technique, there is a problem in that when it is intended to detect the fault with respect to the scanned logic circuit, the time required for the test becomes long, or the area of the chip increases to a great extent.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit capable of decreasing the test cost as compared with the conventional technique by reducing the test time and by suppressing the increase of the chip area.
Another object of the present invention is to provide a manufacturing method of a semiconductor integrated circuit which decreases the test cost by reducing the test time.
There is constituted a scan flipflop (scan latch) as a storage circuit, wherein the storage circuit comprises:
a first logic gate for receiving a first signal and a second signal, and for selectively outputting either the first signal or the second signal in accordance with a control signa
Chang Daniel D.
Miles & Stockbridge P.C.
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