Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-07-31

2004-04-27

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S780000, C257S781000, C257S782000, C257S783000, C257S784000, C257S785000, C257S786000, C257S691000

Reexamination Certificate

active

06727596

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a plurality of input/output buffers for buffering signals inputted/outputted to/from input/output terminals.
BACKGROUND OF THE INVENTION
With a background of highly advanced computerization and society requesting higher precision of information, larger number of bits in a process signal is required. As a result, semiconductor integrated circuits are required to process a greater number of signals. In other words, semiconductor integrated circuits are required to have a large number of input/output signals. Under present circumstances, such a demand is addressed by reducing the size of the semiconductor integrated circuit. In order to reduce the size, however, technical reforms regarding processing are necessary, and considerable time is required to accumulate techniques to achieve the reforms.
FIG. 11
is a schematic configuration diagram of a conventional semiconductor integrated circuit.
FIGS. 12A and 12B
are diagrams for explaining an I/O buffers
131
shown in FIG.
11
. In the conventional semiconductor integrated circuit
100
shown in
FIG. 11
, all the I/O buffers
131
are disposed so that their orientations to a pad P shown in
FIG. 12A
are perpendicular to a dicing lines
150
of the semiconductor integrated circuit
100
.
Each of the I/O buffers
131
is disposed at an outermost portion to make a chip core area
120
wider. Consequently, in the semiconductor integrated circuit
100
, a bump
141
for a signal to be connected to the I/O buffer
131
is disposed in a bump area
121
for signals on the chip core area
120
side. In
FIG. 12A
, reference number
132
denotes a pre-buffer, and
133
indicates a final driver. In
FIGS. 11 and 12A
, reference symbol L
1
and L
2
denote a power source voltage line (“Vdd line”) for supplying a voltage to the final driver
133
and a GND line (“Vss line”), respectively.
In the conventional semiconductor integrated circuit, however, the size of the I/O buffer
131
is under constraints of routing of a line for connecting a bump on the inside and a pad P. The maximum number of I/O buffers
131
which can be mounted on a semiconductor integrated circuit is determined by the chip size. In other words, even if the size of a circuit (such as a gate array) occupying the chip core area
120
is small, the semiconductor integrated circuit has to be large as a whole to assure the necessary number of input/output terminals. Consequently, wasted space is generated in the chip core area
120
.
For example, as shown in
FIG. 12B
, near the I/O buffers
131
arranged in parallel, bumps such as the bump
141
for a signal, a bump
140
for a core power source, a bump
142
for the Vdd line, and a bump
143
for the Vss line are disposed with predetermined positioning relations on bump placement lines BL
1
to BL
9
arranged at predetermined intervals under constraints of the routing of lines. In
FIG. 12B
, due to the constraints, the six bumps
141
for signals on the chip core area
120
are disposed on the bump placement lines BL
4
to BL
9
and the six I/O buffers
131
are connected to each other in a one-to-one corresponding manner. Specifically, under the constraints, the bump placement line BL
9
is the upper limit of the bump placement lines which can be connected to the I/O buffer
131
. The upper limit is not changed even when the width of each I/O buffer
131
is simply reduced.
Further, since all the I/O buffers
131
are oriented perpendicular to the dicing lines
150
of the semiconductor integrated circuit
100
, as shown in
FIG. 11
, free areas
140
are formed at the four corners of the semiconductor integrated circuit
100
.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a semiconductor integrated circuit that can accommodate more I/O buffers without increasing the size. In other words, the object is to provide a semiconductor integrated circuit with a reduced wasted chip core area by changing the positions or orientations of I/O buffers positioning on the same side.
The semiconductor integrated circuit according to one aspect of this invention comprises a plurality of input/output pads provided along a periphery of the semiconductor integrated circuit; a plurality of I/O buffers which buffer signals inputted/outputted to/from the input/output pads; a first bump area for signal constructed by a bump for signal as an input/output bump of a chip core and disposed on a chip core area side with respect to the I/O buffers; and a second bump area for signal constructed by a bump for signal as an input/output bump of the chip core and disposed on the periphery with respect to the I/O buffers. The I/O buffers are disposed in positions sandwiched by the first and the second bump areas, and connected to the bump for signal in the first and second bump areas for signal.
According to the invention, the I/O buffers are disposed in positions sandwiched by the two bump areas for signals, so that the routing of a line from the bump for signal to the I/O buffer can be spread into two directions.
The semiconductor integrated circuit according to another aspect of this invention comprises a plurality of input/output pads provided along a periphery of the semiconductor integrated circuit; a plurality of I/O buffers which buffer signals inputted/outputted to/from the input/output pads, in each of which a first end portion, a power line connection portion, a GND line connection portion, and a second end portion are sequentially placed. The plurality of I/O buffers including a first I/O buffer in which the input/output pad is disposed between the first end portion and the power line connection portion; and a second I/O buffer in which the input/output pad is disposed between the second end portion and the GND line connection portion.
According to the invention, the first and second I/O buffers having the input/output pads positioned relative to each other are provided, according to the presence or absence of a through hole for connecting the power source line and the GND line, the first and second I/O buffers are selectively properly placed. Consequently, it can be prevented that a bypass line is used as the line connecting the input/output pad and the bump.
The semiconductor integrated circuit according to still another aspect of this invention comprises a plurality of input/output pads provided along a periphery of the semiconductor integrated circuit; a plurality of I/O buffers which buffer signals inputted/outputted to/from the input/output pads. The plurality of I/O buffers includes a first I/O buffer constructed by sequentially placing a first end portion, a power line connection portion, a GND line connection portion; and a second end portion and a second I/O buffer constructed by replacing the position of the power line connection portion and the position of the GND line connection portion with each other in the first I/O buffer. A rectangle is formed by disposing the first I/O buffers in parallel in four sides, and the second I/O buffers are disposed at four corners of the rectangle so that the power line connection portion in the second I/O buffer is connected to a power line to be connected to the power line connection portion in the first I/O buffer, and the GND line connection portion in the second I/O buffer is connected to a GND line to be connected to the GND line connection portion in the first I/O buffer.
According to the invention, the second I/O buffers oriented opposite to the first I/O buffers arranged in parallel in the four sides can be disposed at the four corners which are conventionally free areas.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 4947233 (1990-08-01), Aso
patent: 5581109 (1996-12-01), Hayashi et al.
patent: 6091089 (2000-07-01), Hiraga
patent: 6207476 (2001-03-01), Zhao et al.
patent: 6287482 (2001-09-01), Hamura et al.
patent: 6323559 (2001-11-01), Chan et al.
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