Electronic digital logic circuitry – Interface
Reexamination Certificate
2002-10-09
2004-03-30
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
C326S063000, C326S068000, C326S080000, C327S112000, C327S333000
Reexamination Certificate
active
06714047
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular to a circuit having an input buffer, an internal circuit and an output buffer, in which a power supply voltage supplied to the internal circuit is different from power supply voltages supplied to the input and output buffers.
2. Related Art
FIG. 13
shows a circuit configuration of conventional semiconductor integrated circuit. As shown in
FIG. 13
, the semiconductor integrated circuit includes an input circuit
11
for receiving a data signal from outside, an internal circuit
15
for carrying out a processing corresponding to a predetermined function of the semiconductor integrated circuit and an output circuit
13
for generating from a data signal received from the internal circuit
15
a signal to be outputted to a subsequent circuit.
As a whole, a low power supply voltage is preferably supplied to such semiconductor integrated circuit in view of recent demand of low consumption power. When the power supply voltage is decreased, there arises a problem in that sufficient performance of the internal circuit
15
cannot be obtained. Therefore, there is a method that while a high power supply voltage is supplied to the internal circuit, a low power supply voltage is supplied, as an IO power supply, to the input circuit and the output circuit.
For example, in the example shown in
FIG. 13
, a high power supply voltage VDD (e.g., 3.0V) is supplied to the internal circuit
15
. A power supply voltage VDDQ (e.g., 1.8V) which is lower than the power supply voltage VDD is supplied, as a power supply for Input/Output, to the input circuit
11
and the output circuit
13
.
Nevertheless, there arises a problem in that even though low power supply voltage is fed to the input circuit as described above, when an input signal is fed to the input circuit, a threshold of the input signal greatly varies.
SUMMARY OF THE INVENTION
The present invention is developed in order to solve the above drawback and an object of the present invention is to provide a semiconductor integrated circuit which suppresses variation of threshold of input signal at an input circuit in the semiconductor integrated circuit which has the input circuit and an output circuit.
The present invention provides a semiconductor integrated circuit that comprises an input circuit that receives a signal, an internal circuit that applies a predetermined function to the received signal, and an output circuit that outputs the signal applied with the predetermined function. A first power supply voltage and a second power supply voltage which is lower than the first power supply voltage are supplied to the semiconductor integrated circuit from the outside. A voltage obtained by decreasing the first power supply voltage is supplied to the input circuit. The second power supply voltage is supplied to the output circuit. Thus, the power supply for the input circuit is separated from the power supply for the output circuit. Accordingly, an influence of power supply noise that is generated at the output circuit at a moment of outputting the data upon the input circuit can be excluded.
The semiconductor integrated circuit further may comprise a first step-down circuit that decreases the first power supply voltage, and a second step-down circuit that decreases the voltage obtained by the first step-down circuit. The voltage from the first step-down circuit is supplied to the internal circuit, and the voltage from the second step-down circuit is supplied to the input circuit. Thus, the respective desired voltages for the internal circuit and the input circuit can be obtained from the power supply voltage by two step-down circuits.
The voltage from the second step-down circuit may be within a range of a standard to a power supply voltage for input and output. Thus, a suitable voltage can be supplied as the power supply for the input circuit.
The second step-down circuit may comprise an NMOS transistor and decreases a voltage by using a threshold voltage of the NMOS transistor, resulting in easy manufacture of the second step-down.
In the semiconductor integrated circuit, during normal operation, the first power supply voltage may be supplied to the input circuit, while during an operation in a power down mode which is an operational mode for reducing current consumption within the integrated circuit, the second power supply voltage may be supplied to the input circuit. Thus, during the power down mode operation, generation of leak current due to variation of the power supply voltage can be suppressed, thereby achieving lower power consumption.
The semiconductor integrated circuit may further comprise a selection circuit that selects, as a power supply to be supplied to the input circuit, one of the first power supply voltage and the voltage which is obtained by decreasing the first power supply voltage. Thus, the semiconductor integrated circuit operable with two types of IO power supplies can be provided.
The input circuit may comprise a first buffer circuit that receives the first power supply voltage to operate and a second buffer circuit that receives the voltage obtained by decreasing the first power supply voltage to operate. The selection circuit may select one of these buffer circuits according to a power supply supplied to the input circuit. By selecting an appropriate buffer circuit depending on the power supply voltage, a more appropriate circuit depending on the power supply voltage can be operated in the semiconductor integrated circuit.
The selection circuit may select the power supply by a selection signal which is generated by electrically connecting an inner lead connected to a predetermined potential to a pad. Thus, the selection signal for controlling the selection circuit can be easily generated.
The selection circuit may select the power supply by a selection signal which is generated based on predetermined data recorded in a rewritable storage.
The rewritable storage may be provided within another integrated circuit but is molded in the same package or one chip.
The selection circuit may select the power supply by a selection signal which is generated in accordance with electrical disconnection of a fuse.
REFERENCES:
patent: 6166580 (2000-12-01), Sessions
patent: 6255888 (2001-07-01), Satomi
patent: 6501306 (2002-12-01), Kim et al.
patent: 7-282585 (1995-10-01), None
Shimizu Tadayuki
Takatsuka Takafumi
Tsukude Masaki
McDermott & Will & Emery
Renesas Technology Corp.
Tan Vibol
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