Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-09-06

2004-03-16

Zarabia, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S173000, C257S355000, C257S356000, C257S357000, C257S358000, C257S360000, C257S361000, C257S363000

Reexamination Certificate

active

06707109

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor integrated circuit device and more specifically to a semiconductor integrated circuit device that prevents damage caused by electrostatic discharge from a charged device model (CDM).
BACKGROUND OF THE INVENTION
As semiconductor device features become finer and the integration of such devices increases, an important concern can be electrostatic discharge (ESD). Electrostatic discharge can result when a static electricity, or the like, is discharged into or from a semiconductor device. ESD may result in damage to a semiconductor device, causing such a device to immediately fail, or have decreased reliability. One particular failure mechanism can be a breakdown of the gate dielectric in an insulated gate field effect transistor (IGFET), such as the gate oxide of a metal-oxide-semiconductor (MOS) FET.
ESD is believed to occur at various stages in a manufacturing process when semiconductor devices are handled and transported, for example.
Various models of the ESD breakdown phenomenon have been proposed, including a human body model (Human Body Model: HBM), a machine model (Machine Model: MM), and a charged device model (Charged Device Model: CDM).
In the HBM, electric charges are generated, and then discharged to a device when a charged human makes contact with the device. In the MM, electric charges are generated on a metal instrument, or the like, and then discharged to a semiconductor device when the instrument and device contact one another. In general, such a metal instrument can have a larger electrostatic capacitance than a human body, but also have a lower discharge resistance than a human body. In the HBM and the MM, the static electricity is applied to or discharged from two specific terminals of the device.
The theory of damage caused by static electricity in the CDM will now be explained.
Referring now to
FIG. 6
, an internal circuit structure of a conventional semiconductor integrated circuit is set forth. A terminal of the semiconductor integrated circuit
114
is connected to a gate of a MOS transistor
112
in the internal circuit. A static electricity protection element
103
is connected between a terminal
102
and a reference electric potential connection
101
. Generally, reference potential connection
101
is a circuit board electric potential connection which differs from a ground (GND) electric potential connection and has a potential different from a GND electric potential.
Static electricity protection element
103
prevents damage to MOS transistor
112
which may be caused by the application of static electricity to terminal
102
. Static electricity protection element
103
provides protection against damage under the human body model (HBM) and machine model (MM).
A capacitance
113
is connected between the chip and ground. Capacitance
113
indicates an equivalent capacitance between the chip and ground in a CDM test which charges the test device and then discharges the electric charge from a specific terminal connected to ground. In this way, the electric charge of the charged chip is stored. Terminal
102
is connected to ground through a CDM test switch
115
. The eclectic charge of the device (the entire electric charge of the chip) is discharged from terminal
102
through reference electric potential connection
101
and static electricity element
103
to ground.
At that time, electric charge stored at the gate of MOS transistor
112
connected to terminal
102
is also discharged to ground. The electric charge stored at the gate of MOS transistor
112
is significantly smaller than that discharged from reference electric potential connection
101
and is thus discharged in a short time.
As a result, the difference in electric potential occurring between the source and gate of MOS transistor
112
increased and the gate insulation (oxide) can be damaged. To prevent this damage under the CDM, a protection element
116
is provided close to and between the gate and source of MOS transistor
112
. This technique is disclosed in “Electrical Overstress/Electrostatic Discharge Symposium Proceeding”, Sep. 27-29, 1988, pp. 220-227.
Referring now to
FIG. 7
, a conventional ESD protection technique is set forth in a block schematic diagram. The conventional ESD protection technique employs a board electric potential connection as the reference potential connection
101
and sets the board electric potential connection
101
to the ground electric potential. Static electricity protection elements
103
are connected to a VCC terminal, an input terminal, and an I/O terminal. Each static electricity protection element
103
is the same as static electricity protection element
103
illustrated in FIG.
6
. In
FIG. 7
, the internal circuit elements and the CDM protection element which are connected to the input terminal are omitted to avoid unduly cluttering the figure. Because the board electric potential connection
101
is connected to the semiconductor board at a number of connections, the electric charge stored in the board can be discharged through the board electric potential connection
101
(reference electric potential connection), protection element
103
, and one test terminal (can be any of terminals
102
) to ground. Thus, protection elements
103
may prevent damage.
Referring now to
FIG. 8
, the conventional ESD protection technique of
FIG. 7
is set forth in a block schematic diagram illustrating the connection of a board electric potential generating circuit
104
. The configuration of
FIG. 8
is similar to
FIG. 7
in that terminals
102
are connected to the board electric potential connection
101
through the static protection elements
103
. Also illustrated is a board electric potential generating circuit
104
connected to the board electric potential connection
101
to generate the board electric potential. Likewise, the electric charge stored in the chip is discharged through the board electric potential connection
101
, protection element
103
, and one test terminal (can be any of terminals
102
) to ground. Thus, protection elements
103
may prevent damage.
This type of conventional technique is disclosed in Japanese Unexamined Patent Application, First publication No. 3-72666 (JPA 3-72666). In JPA 3-72666, static electric pulses applied to terminals are discharged through a plurality of protection elements, an electric power connection, and a reference electric potential connection. Japanese Patent No. 2,848,674 discloses a single connection, which connects terminals through the protection element. Japanese Patent No. 2,972,494 discloses a single connection, which connects the terminals through the protection element. Thus, charge is allowed to discharge in either direction between two terminals depending on the application of either a positive or negative voltage.
Japanese Patent No. 2,910,474 discloses a protection element between an internal power source connection and a reference electric potential connection to a circuit for increasing or decreasing an internal power voltage.
In these publications, the protection element is provided between the input/output terminal and the reference electric potential connection or between the power source connections at different electric potentials.
Referring now to
FIG. 9
, a conventional ESD protection technique is set forth in a block schematic diagram. In the semiconductor integrated circuit illustrated in
FIG. 9
, the reference electric potential connection
101
is connected to the ground potential. In this case the board electric potential generating circuit
104
is connected to the board electric potential connection
106
and there is no path for discharging the charge stored in the board in the CDM test, thereby decreasing the CDM tolerance.
The above-mentioned publications disclose static electricity protection elements as shown in FIG.
9
and disclose different structures related to the reference electric potential connection
101
and board electric potential connection
106
. In the

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