Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2002-12-24

2004-07-06

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S093000, C326S121000, C327S208000, C327S214000

Reexamination Certificate

active

06759876

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a logic circuit.
In recent semiconductor integrated circuits, a high operation speed, area reduction, small power consumption and the like have been realized by refining the fabrication processes. When the gate length of a transistor is reduced by refining the process, a drain current per unit gate width of the transistor flowing when the transistor is in an on state is advantageously increased. On the other hand, a leakage current flowing between the drain and the source when the transistor is in an off state (hereinafter referred to as the subthreshold current) is disadvantageously increased. The increase ratio of the subthreshold current involved in the refinement is larger than the increase ratio of the drain current flowing when the transistor is in an on state.
FIG. 11
is a circuit diagram for showing an example of conventional dynamic semiconductor integrated circuits. The circuit of
FIG. 11
includes PMOS transistors
2101
and
2102
, an input circuit
2120
and an output circuit
2130
. The input circuit
2120
includes NMOS transistors
2121
and
2122
, and the output circuit
2130
includes a PMOS transistor
2131
and an NMOS transistor
2132
. The circuit of
FIG. 11
obtains and outputs a logical OR between input signals VI
1
and VI
2
.
A period when a clock signal CLK is at “L” level (namely, at a low logic level) corresponds to a precharge period. In this period, the PMOS transistor
2101
is turned on so as to precharge a node N
211
. The input signals VI
1
and VI
2
are kept at “L” level.
A period when the clock signal CLK is at “H” level (namely, a high logic level) corresponds to an evaluation period. In this period, the input signals VI
1
and VI
2
are activated. When one of the input signals VI
1
and VI
2
undergoes a “L” to “H” transition, the node N
211
is discharged, and hence, an output signal V
21
undergoes a “L” to “H” transition. When both the input signals VI
1
and VI
2
are at “L” level, the node N
211
is not discharged, and hence, the output signal V
21
is at “L” level. At this point, the PMOS transistor
2102
is in an on state so as to keep the potential of the node N
211
at “H” level.
FIG. 12
is a circuit diagram for showing an example of conventional static semiconductor integrated circuits. The circuit of
FIG. 12
functions as a buffer circuit in which two stages of inverters are serially connected to each other. The circuit of
FIG. 12
includes an inverter having a PMOS transistor
2231
and an NMOS transistor
2232
, and an inverter having a PMOS transistor
2281
and an NMOS transistor
2282
.
With respect to the dynamic circuit having the configuration shown in
FIG. 11
, the case where the subthreshold current flowing when a transistor is in an off state becomes too large to ignore as compared with the drain current flowing when the transistor is in an on state will now be described.
In the evaluation period, even when both the input signals VI
1
and VI
2
are at “L” level, the subthreshold current flows through the NMOS transistors
2121
and
2122
. At this point, the current flows from the power supply through the PMOS transistor
2102
and the NMOS transistor
2121
or
2122
to a ground line. In this case, the potential of the node N
211
is lower than supply potential VDD by a voltage Vd.
At this point, when the voltage Vd is smaller than the threshold voltage Vt (that is, a gate-source voltage obtained when a transistor is switched from an off state to an on state) of the PMOS transistor
2131
, the PMOS transistor
2131
is turned off and the NMOS transistor
2132
is turned on, so that the output signal V
21
can be at “L” level. The potential of this output signal V
21
is higher than ground potential VSS. Assuming that the PMOS transistor
2131
has a resistance value R
2131
and the NMOS transistor
2132
has a resistance value r
2132
, a shift Vdo of the potential of the output signal V
21
from the ground potential VSS is VDD*r
2132
/(R
2131
+r
2132
).
Alternatively, when the voltage Vd is larger than the threshold voltage Vt of the PMOS transistor
2131
, this transistor is turned on. Since both the PMOS transistor
2131
and the NMOS transistor
2132
are in an on state, not only the output is undefined but also a large through current unavoidably flows through these transistors.
Also in the precharge period, when the subthreshold current flows through the NMOS transistors
2121
and
2122
, the potential of the node N
211
becomes lower than the supply potential VDD, and hence, a similar problem occurs.
Since the subthreshold current has a property to exponentially increase against the gate-source voltage Vgs of the transistor, when the gate-source voltage Vgs of the PMOS transistor
2131
is equal to the voltage Vd, a larger current flows through this transistor than when the voltage Vgs is 0, which increases the shift Vdo of the potential of the output signal V
21
.
In this manner, when the subthreshold current is too large to ignore, the shift of the potential of the output signal V
21
, namely, DC noise to be output, becomes too large to ignore. In particular, when DC noise included in an output signal is larger than DC noise included in an input signal, this means that the DC noise is amplified.
Such a phenomenon is described in “A Conditional Keeper Technique for Sub-0.13&mgr; Wide Dynamic Gates” (Atila Alvandpour et. al., 2001 Symposium on VLSI Circuits Digest of Technical Papers 3-4).
When a plurality of such circuits that amplify DC noise included in an input signal are serially connected to one another, the DC noise is gradually increased, resulting in the malfunction of the circuit. Also, even when the circuit does not amplify DC noise, if the voltage Vd and the shift Vdo of the potential of the output signal V
21
are large, a leakage current flowing between the power supply and the ground line is exponentially increased, and hence, the power consumed when the transistor is in an off state becomes disadvantageously large.
Also in the static circuit having the configuration shown in
FIG. 12
, in the case where the subthreshold current flowing when a transistor is in an off state is too large to ignore as compared with the drain current flowing when the transistor is in an on state, a similar problem occurs.
Specifically, since the subthreshold current flows through the PMOS transistor
2231
, even when an input signal VI is at “H” level, the potential of the node N
221
is higher than the ground potential VSS. Therefore, the potential of an output signal V
22
is lower than the supply potential VDD, namely, the output signal V
22
includes DC noise. When DC noise included in the output signal is larger than DC noise included in the input signal, this means that the DC noise is amplified. Also when a plurality of such circuits that amplify DC noise included in an input signal are serially connected to one another, the malfunction of the circuit is caused.
SUMMARY OF THE INVENTION
An object of the invention is providing a semiconductor integrated circuit for outputting a signal with small DC noise.
Specifically, the first semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting the first node at a second logic level different from the first logic level in accordance with an input signal; a second transistor for setting a second node at the first logic level when the first node is at the first logic level; a first resistor device that is connected between the first node and the second node and has a large resistance value when the first node is at the first logic level and has a small resistance value when the first node is at the second logic level; a first driving transistor for receiving, as an input, potential of the second node and controlling whether or not an output node is set at the first logic level; and a second

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