Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-12-07
2003-10-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S034000, C326S036000, C326S119000, C326S121000, C326S093000, C326S095000, C326S098000, C327S206000, C327S216000
Reexamination Certificate
active
06636073
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and a method for analyzing C-V (Capacitance-Voltage) characteristics of a MIS (Metal/Insulator/Semiconductor) structure, and more particularly to an apparatus and a method which can analyze C-V characteristics of a MIS structure including a thin film silicon oxide having the thickness of less than 3 nm.
2. Description of the Related Art
Conventionally, in the case where a logic circuit provided in a semiconductor integrated circuit includes devices a threshold voltage of which is low so as to operate the semiconductor integrated circuit at a low voltage, there is a problem that a leakage current in the semiconductor integrated circuit is increased when the semiconductor integrated circuit is on standby. Japanese Laid-Open Publication No. 6-29834 discloses a logic circuit which includes devices having a high threshold voltage as well as devices having a low threshold voltage, so that a leakage current in a semiconductor integrated circuit including such a logic circuit is decreased when the semiconductor integrated circuit is on standby. An embodiment of this conventional technology is described below with reference to FIG.
10
.
FIG. 10
is a circuit diagram illustrating a schematic structure of a conventional semiconductor integrated circuit. The conventional semiconductor integrated circuit includes an inverter logic circuit I
100
. The inverter logic circuit I
100
is connected to a drain of a PMOSFET m
100
at its high potential power terminal and is connected to a drain of an NMOSFET m
101
at its low potential power terminal. A source of the PMOSFET m
100
is connected to a power line Vdd and a source of the NMOSFET m
101
is connected to a ground line GND. The PMOSFET m
100
receives a control signal CSB at its gate. The NMOSFET m
101
receives a control signal CS at its gate. The control signal CS is generated by inverting the control signal CSB.
The inverter logic circuit I
100
includes MOSFETs (not shown) having a low threshold voltage so as to operate the inverter logic circuit I
100
at a low voltage. A threshold voltage of each of the PMOSFET m
100
and the NMOSFET m
101
is high. In the inverter logic circuit I
100
, which is on standby, when a HIGH-state control signal CS and a LOW-state control signal CSB are input to the PMOSFET m
100
and the NMOSFET m
101
, respectively, both of the PMOSFET m
100
and the NMOSFET m
101
are turned on. At this point, the inverter logic circuit I
100
is electrically connected via the PMOSFET m
100
to the power line Vdd and is electrically connected via the NMOSFET m
101
to the ground line GND. The inverter logic circuit I
100
is operated at a low power voltage since the inverter logic circuit I
100
includes the MOSFETs having a low threshold voltage.
In the inverter logic circuit I
100
, which is on standby, when the LOW-state control signal CS and the HIGH-state control signal CSB are input to the PMOSFET m
100
and the NMOSFET m
101
, respectively, both of the PMOSFET m
100
and the NMOSFET m
101
are turned off. At this point, the inverter logic circuit I
100
is electrically disconnected from the power line Vdd and the ground line GND, so that the inverter logic circuit I
100
is not operated. A leakage current in the inverter logic circuit I
100
is kept low since the threshold voltage of each of the PMOSFET m
100
and the NMOSFET m
101
a
is low.
Next, referring to
FIG. 11
, a conventional technology for controlling a substrate potential of a SOI (silicon on insulator) device so as to operate the SOI device at a low voltage and keep a low leakage current in the SOI device is described below.
FIG. 11
is a circuit diagram illustrating a conventional inverter logic circuit. This conventional inverter logic circuit includes a PMOSFET m
102
and an NMOSFET m
103
. A source of the PMOSFET m
102
is connected to a power line Vdd. A gate of the PMOSFET m
102
and a gate of the NMOSFET m
103
are connected to each other and an input terminal S
1
of the conventional inverter logic circuit. A drain of the PMOSFET m
102
and a drain of the NMOSFET m
103
are connected to each other and an output terminal S
2
of the conventional inverter logic circuit. A body (or a backgate when the conventional inverter logic circuit has a bulk structure) of the PMOSFET m
102
is connected to the input terminal S
1
.
A source of the NMOSFET m
103
is connected to a ground line GND. The gate of the NMOSFET m
103
is connected to the input terminal S
1
. The drain of the NMOSFET m
103
is connected to the drain of the PMOSFET m
102
and the output terminal S
2
. A body (or a backgate when the conventional inverter logic circuit has a bulk structure) of the NMOSFET m
103
is connected to the input terminal S
1
.
When a state of a control signal input via the input terminal S
1
is changed from LOW to HIGH, a body (substrate) potential of the NMOSFET m
103
is also changed from LOW to HIGH, so that a threshold voltage of the NMOSFET m
103
is decreased. Thus, the NMOSFET m
103
is rapidly turned on and is operated at high speed.
In this case, a gate potential and a body potential of the PMOSFET m
102
are changed from LOW to HIGH, and the PMOSFET m
102
is turned off, so that a threshold voltage of the PMOSFET m
102
is increased. Similarly, when a state of a control signal input to the PMOSFET m
102
is changed from HIGH to LOW, a body potential of the PMOSFET m
102
is changed from LOW to HIGH, so that a threshold voltage of the PMOSFET m
102
is decreased. Thus, the PMOSFET m
102
is rapidly turned on and is operated at high speed.
In this case, a gate potential and a body potential of the NMOSFET m
103
are changed from HIGH to LOW, and the NMOSFET m
103
is turned off, so that a threshold voltage of the NMOSFET m
103
is increased. In this manner, the threshold voltage of each of the PMOSFET m
102
and the NMOSFET m
103
is decreased when the PMOSFET m
102
and the NMOSFET m
103
are turned on and is increased when the PMOSFET m
102
and the NMOSFET m
103
are turned off, and thus the SOI device can be operated at a low voltage, and a leakage current in the SOI device can be kept low.
However, the above-described conventional technologies have the following problems.
In the conventional technology described with reference to
FIG. 10
, it is necessary to include MOSFETs having a high threshold voltage in the semiconductor integrated circuit in order to decrease a leakage current in the semiconductor integrated circuit when the semiconductor integrated circuit is on standby. Specifically, in order to operate the semiconductor integrated circuit at a low voltage and maintain a low leakage current in the semiconductor integrated circuit, it is necessary to form MOSFETs, each operable at a threshold voltage differing from that of the other, on the same semiconductor substrate. However, this results in a complicated production process of the semiconductor integrated circuit. Moreover, a control signal is required to be input to the semiconductor integrated circuit so as to cause the semiconductor integrated circuit to be on standby, and when the semiconductor integrated circuit is on standby, a logic circuit provided in the semiconductor integrated circuit is electrically disconnected from a power source and is not operated. Therefore, it is not appropriate to apply the conventional technology to a circuit (e.g., a flip-flop circuit, a memory, etc.) for storing data.
In the conventional technology described with reference to
FIG. 11
, it is necessary to provide electrodes connected to MOSFET bodies in the semiconductor integrated circuit in order to change a body potential of the MOSFETs, and thus a total area of the semiconductor integrated circuit is increased. Since it is necessary to control the body potential of the MOSFETs, this conventional technology can only be applied to PD-type (partial depletion-type) FETs and cannot be applied to FD-type (full depletion-type) FETs.
SUMMARY OF THE INVENTION
A semiconductor integrated circuit accord
Sharp Kabushiki Kaisha
Tan Vibol
Tokar Michael
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