Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-12-10

2003-09-02

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S121000, C326S017000

Reexamination Certificate

active

06614266

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which the level of a node of the circuit during the standby mode is not uniquely determined and the sub-threshold leaking current across the node is reduced by taking the countermeasures so as to reduce the standby power consumption.
2. Description of the Related Art
It is known that complementary metal-oxide semiconductor (CMOS) circuits, such as the semiconductor integrated circuit, exhibit extremely low standby power.
For the sake of simplicity of description, suppose a simple CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor. In such CMOS circuit, when the input signal is set to the high level, the p-channel transistor is set in OFF state and the n-channel transistor is set in ON state. After the discharging of a capacitive load at the output of the CMOS circuit is performed, the n-channel transistor is set in OFF state. Normally, in this condition, the power consumption of the CMOS circuit is negligible.
When the input signal is set to the low level, the p-channel transistor is set in ON state and the n-channel transistor is set in OFF state. After the discharging of the capacitive load at the output of the CMOS circuit is performed, the p-channel transistor is set in OFF state. Normally, in this condition, the power consumption of the CMOS circuit is also negligible.
However, the level of integration of semiconductor integrated circuits is further increased from that of the conventional version with the recent developments of micro-fabrication technology used in CMOS circuits. When compared to a MOS transistor with the channel length of 1 &mgr;m, a MOS transistor with the channel length of 0.1 &mgr;m has a lower threshold voltage, and the drain current is not zero if the gate voltage (or the gate-to-source voltage) is less than the threshold voltage. Hereinafter, the drain current which leaks from the MOS transistor in the region in which the gate voltage is less than the threshold voltage is called the sub-threshold leaking current, and the region in which the gate voltage is less than the threshold voltage is called the sub-threshold region. This sub-threshold leaking current exponentially increases to the gate voltage.
Hence, the increase of the sub-threshold leaking current described above is detrimental to the demand for providing a semiconductor integrated circuit that exhibits low power consumption. Specifically, the power consumption of a semiconductor integrated circuit, including MOS transistors produced by the micro-fabrication method, during the standby mode depends on the amount of the sub-threshold leaking current. In order to reduce the power consumption, it is necessary to reduce the sub-threshold leaking current.
On the other hand, an improved semiconductor integrated circuit has been proposed, and, in this circuit, the sub-threshold leaking current is reduced by taking the countermeasures so as to reduce the standby power consumption. This semiconductor integrated circuit includes an internal circuit having MOS transistors produced by the micro-fabrication method. To prevent the lowering of the breakdown voltage of such MOS transistors, a voltage lowering circuit is provided to generate a lowered power-source voltage from an external power-source voltage. The voltage lowering circuit supplies the lowered power-source voltage to the MOS transistors of the internal circuit, thereby reducing the sub-threshold leaking current.
FIG. 1
shows a semiconductor integrated circuit in which a conventional method for reducing the sub-threshold leaking current is incorporated. Regarding the conventional method in
FIG. 1
, Japanese Laid-Open Patent Application No. 5-210976 discloses a similar method to reduce the sub-threshold leaking current.
As shown in
FIG. 1
, the semiconductor integrated circuit includes a logic circuit
100
, a switching device
101
, a switching device
102
, and a target circuit
107
. In the present example, the target circuit
107
is the circuit to which the countermeasure against the sub-threshold leaking current is to be taken.
In
FIG. 1
, “Viiz” and “Vssx” indicate the power-source lines which deliver the power-source voltages to reduce the sub-threshold leaking current, and “Vii” and “Vss” indicate the power-source lines which deliver the power-source voltages. When the semiconductor integrated circuit of
FIG. 1
is set in the active mode, the voltage of the power-source line “Viiz” is the same as the voltage of the power-source line “Vii”. When the semiconductor integrated circuit of
FIG. 1
is set in the standby mode, the voltage of the power-source line “Viiz” is set in a floating state. Hereinafter, the “Viiz” and “Vssx” are called the countermeasure voltage lines, and the power-source voltage lines “Vii” and “Vss” are called the normal voltage lines, for the sake of convenience of description.
In the semiconductor integrated circuit of
FIG. 1
, the switching device
101
connects the countermeasure voltage line Viiz with the normal voltage line Vii. The switching device
102
connects the countermeasure voltage line Vssx with the normal voltage line Vss. The logic circuit
100
receives input signals and performs a logic operation for the input signals. A standby mode signal “stbx” indicates whether the integrated circuit is set in the standby mode, and this standby mode signal is input to the logic circuit
100
. In response to the standby node signal “stbx”, the logic circuit
100
respectively outputs signals “n
101
” and “n
102
” to the switching devices
101
and
102
through the logic operation. Namely, when the integrated circuit is set in the standby mode, the switching devices
101
and
102
are set in OFF state by the output signals “n
101
” and “n
102
” of the logic circuit
100
. When the integrated circuit is set in the active mode, the switching devices
101
and
102
are set in ON state by the output signals “n
101
” and “n
102
” of the logic circuit
100
.
In the semiconductor integrated circuit of
FIG. 1
, the switching devices
101
and
102
are constructed by using high-threshold transistors. The switching devices
101
and
102
serve to provide the countermeasure power-source voltages of the voltage lines “Viiz” and “Vssx” from the normal power-source voltages of the voltage lines “Vii” and “Vss”. Because of the high-threshold structure of the transistors
101
and
102
, the sub-threshold leaking current across each of the transistors
101
and
102
during the standby mode is virtually negligible.
In the semiconductor integrated circuit of
FIG. 1
, the target circuit
107
is comprised of two simple inverters that are concatenated, the first inverter including a p-channel MOS transistor
103
and an n-channel MOS transistor
104
, and the second inverter including a p-channel MOS transistor
105
and an n-channel MOS transistor
106
. An input signal “n
103
”, the level of which is uniquely determined during the standby mode, is supplied to the inputs of the transistors
103
and
104
of the target circuit
107
.
Suppose that the input signal “n
103
” is set at the low level when the integrated circuit is set in the standby mode. When the input signal “n
103
” is at the low level, the transistor
103
is set in ON state, and the transistor
104
is set in OFF state. In this condition, the sub-threshold leaking current may occur at the transistor
104
. To avoid this, the countermeasure is taken such that the source of the transistor
103
is connected to the normal voltage line “Vii” and the source of the transistor
104
is connected to the countermeasure voltage line “Vssx”. During the standby mode, the switching device
102
is set in OFF state, the source of the transistor
104
is disconnected from the normal voltage line “Vss” due to the OFF state of the switching device
102
, and the sub-threshold leaking current which tends to flow through the source/drain path of the transistor
104
is avoided by the connection of the source of t

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