Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-04-13
2003-03-04
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S121000
Reexamination Certificate
active
06529042
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates a semiconductor integrated circuit, particular a semiconductor integrated circuit suitable for very large-scale integrated circuits (VLSIs), etc.
2. Description of the Prior Art
Recently, battery driven VLSIs for portable terminals such as cellular phones have rapidly increased in number. It is indispensable for such battery driven VLSIs that power consumption is small. There are methods to suppress the power consumption by suppressing leakage current in the stand-by period.
MTCMOS is one of the methods, which can suppress the leakage current in the stand-by period. In the MTCMOS, a power switch is connected in series to a CMOS circuit and a threshold voltage of a metal oxide semiconductor field effect transistor (hereafter, often abbreviated to a “MOSFET”) is higher than that of a MOSFET constituting the CMOS circuits.
Therefore, the threshold current in the stand-by period is suppresses through the high threshold voltage of the power switch and the power consumption is reduced. Moreover, high-speed operation of the circuit can be achieved through the relatively low threshold voltage of the CMOS circuit.
In MTCMOS, when a supply voltage becomes low, its speed is degraded due to the high threshold voltage of the power switch. In order to compensate this problem, the gate width of the power switch has to be enlarged.
However, the enlargement of the gate width increases the area of the power switch. Thus, the area penalty of the power switch is increased, resulting in the degradation of the integrated density of the whole circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a new semiconductor integrated circuit in which a CMOS circuit and a switch are connected in series, which has high drivability and high integration density through the reduction of the area penalty of the switch.
This invention relates to a semiconductor integrated circuit (hereinafter, often called as a “first semiconductor integrated circuit”) in which a CMOS circuit composed of a first MOSFET and a switch composed of a second MOSFET are connected in series and a switch-driving voltage to drive the switch is higher than a circuit-driving voltage to drive the CMOS circuit.
The inventors have been intensely studied to achieve the above object.
As a result, they have conceived that besides the circuit-driving voltage to drive the CMOS circuit, corresponding to what is called the supply voltage, a switch-driving voltage is applied to the switch. Then, they found that when the switch-driving voltage is higher than the circuit-driving voltage, the speed of the circuit improves. Therefore, even in the case of smaller gate width of the switch for the reduction of the area penalty, the speed of the circuit is not degraded.
Consequently, using the present invention, a semiconductor integrated circuit, which has not only high speed but also high integration density, can be realized.
This invention also relates to a semiconductor integrated circuit (hereinafter, often called as a “second semiconductor integrated circuit”) in which a CMOS circuit composed of a first MOSFET and a switch composed of a second MOSFET are connected in series and a negative switch-biasing voltage is applied to the switch.
The inventors have studied more intensely to find out another method to achieve the above object. As a result, they found that by using a negative switch-biasing voltage the above object could be realized.
The first semiconductor integrated circuit is realized in the devise of the driving force at the driving condition of the whole circuit. On the contrary, the second semiconductor integrated circuit is realized in the devise of the circuit itself at the halt condition of the whole circuit.
In the stand-by period, the voltage of the switch is generally fixed to 0 V. On the other hand, in the semiconductor integrated circuit of the present invention, the negative switch-biasing voltage is willingly applied to the switch at the stand-by period.
Because applying the negative switch-biasing voltage to the switch can reduce the threshold current of the switch, the threshold voltage of the switch can be lowered and the effective switch-driving voltage can be increased. For example, when −0.3 V is applied to the switch in the stand-by period, the threshold voltage of the switch can be lowered by 0.3 V. The effective switch-driving voltage is the difference between the switch-driving voltage and the threshold voltage of the switch. Therefore, in this case, the effective applied voltage to the switch is increased by 0.3 V.
As mentioned above, by applying the negative voltage to the switch in the stand-by period, the threshold voltage of the switch can be lowered and the effective switch-driving voltage can be increased, hence the speed of the circuit can be enhanced. Therefore, even though the area penalty of the switch is decreased, the speed of the circuit is not degraded. That is, the semiconductor integrated circuit having a high integration density can be obtained with maintaining the speed of the whole circuit.
This invention is not limited to a semiconductor integrated circuit such as MTCMOS in which a switch has a higher threshold voltage than a CMOS circuit. The semiconductor integrated circuit, in which a CMOS and a switch have the same threshold voltage, also faces the degradation of the speed when the supply voltage is low. Because the present invention can also improve the speed such a semiconductor integrated circuit, it is usable for every kind of semiconductor integrated circuit.
REFERENCES:
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 5680071 (1997-10-01), Senoh et al.
patent: 5990516 (1999-11-01), Momose et al.
patent: 10-303370 (1998-11-01), None
patent: 410335608 (1998-12-01), None
patent: 11-340806 (1999-12-01), None
Hiramoto Toshiro
Inukai Takashi
Sakurai Takayasu
Chang Daniel D.
Oliff & Berridg,e PLC
University of Tokyo
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