Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2002-01-22

2003-09-09

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S083000, C326S090000, C326S082000, C326S030000, C327S108000

Reexamination Certificate

active

06617881

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit that forms a differential output circuit for outputting signals to another semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
FIG. 1
shows a differential output circuit based on the conventional art. This differential output circuit comprises two n-channel MOS transistors (hereafter called nMOS transistor) M
1
and M
3
, two p-channel MOS transistors (hereafter called pMOS transistor) M
2
and M
4
, two constant current sources J
1
, J
2
, and drivers IN
1
, IN
2
, BU
1
, and BU
2
. The drivers IN
1
, IN
2
, BU
1
, and BU
2
receive a common input signal X to generate control signals A
1
, A
2
, B
1
, and B
2
to be applied to respective gate electrodes of the MOS transistors M
1
to M
4
. When the input signal X is at a low level (hereafter called L level), the transistors M
1
and M
4
are turned on, while the transistors M
2
and M
3
are turned off. Conversely, when the input signal X is at a high level (hereafter called H level), the transistors M
1
and M
4
are turned off, while the transistors M
2
and M
3
are turned on. Accordingly, logical signals Y
1
and Y
2
in opposite phases to each other are output from nodes N
1
and N
2
, respectively.
The output signals Y
1
and Y
2
are transferred to circuits of another semiconductor chip through respective transmission paths
1
and
2
. A resistor R is connected between the nodes N
1
and N
2
to perform a function as a terminator resistor with respect to the transmission paths
1
and
2
.
Each of the drivers IN
1
and IN
2
is a CMOS inverter circuit that outputs an inverted logic of an input signal X. Each of the drivers BU
1
and BU
2
consists of two CMOS inverter circuits connected in series, and is a buffer circuit for outputting the same logic as that of an input signal X.
FIG. 2
shows respective waveforms of the control signals A
1
, A
2
, B
1
, and B
2
and the output signals Y
1
and Y
2
. Assume that the drivers IN
1
and IN
2
have changed from an H level to an L level at a time s
1
in response to a change of an input signal X from an L level to an H level. Because of the difference of configuration of the drivers BU
1
and BU
2
from that of the drivers IN
1
and IN
2
, the signals B
1
and B
2
change from the L level to the H level at a time s
2
that is later than the time s
1
as shown in FIG.
2
.
The MOS transistor M
1
changes from an on state to an off state and the MOS transistor M
2
changes from an off state to an on state in response to level changes of the signals A
1
and A
2
at the time s
1
, respectively, and the voltage on the node N
1
then rises from the L level. On the other hand, the MOS transistor M
3
remains in the off state and the MOS transistor M
4
remains in the on state until the time s
2
is reached. Therefore, the potential on the node N
2
also rises through the resistor R according to rising of the voltage on the node N
1
. Subsequently, the MOS transistors M
3
and M
4
change to the on state and the off state, respectively, in response to level changes of the signals B
1
and B
2
at the time s
2
, and the voltage on the node N
2
drops. In response to the drop, the voltage on the node N
1
momentarily drops through the resistor R, but the node N
1
is driven by the MOS transistor M
2
to the high voltage again.
When the signals A
1
and A
2
change from the L level to the H level at a time s
3
in response to a change of the input signal X from the H level to the L level, the signals B
1
and B
2
change from the H level to the L level at a time s
4
that is later than the time s
3
. The MOS transistor M
1
changes from the off state to the on state and the MOS transistor M
2
changes from the on state to the off state in response to level changes of the signals A
1
and A
2
at the time s
3
, and the voltage on the node N
1
drops from the H level. On the other hand, the MOS transistor M
3
remains in the on state and the MOS transistor M
4
remains in the off state until the time s
4
is reached. Therefore, the potential on the node N
2
also drops through the resistor R according to drop of the voltage on the node N
1
. The MOS transistor M
3
changes to the off state and the MOS transistor M
4
changes to the on state in response to level changes of the signals B
1
and B
2
at the time s
4
, respectively, and the voltage on the node N
2
rises. The voltage on the node N
1
momentarily rises through the resistor R according to rising of the voltage on the node N
2
, but the node N
1
is driven by the MOS transistor M
1
to the low voltage again.
As explained above, the control signals A
1
, A
2
, B
1
, and B
2
are generated so that response of the signals B
1
and B
2
to the input signal X is delayed as compared to response of the signals A
1
and A
2
. Resultantly, as shown in
FIG. 2
, an overshoot that momentarily exceeds the voltage at the H level and an undershoot that momentarily drops lower than the voltage at the L level occur in the output signal Y
2
in response to logical level changes of the input signal X. Further, a portion D
1
that momentarily drops its waveform and a portion D
2
that momentarily raises its waveform occur in the output signal Y
1
. The distortions of these waveforms are caused by occurrence of a period in which both of the MOS transistors M
1
and M
2
are turned off simultaneously when both of the MOS transistors M
3
and M
4
are turned on or by occurrence of a period in which both of the MOS transistors M
3
and M
4
are turned off simultaneously when both of the MOS transistors M
1
and M
2
are turned on according to level changes of the input signal X.
Such distortions in the output waveforms of the output signals Y
1
and Y
2
are not merely an apparent problem but become a problem in terms of signal propagation property. For example, although the terminator resistor R is provided, the signals Y
1
and Y
2
are reflected to a certain extent by the respective ends of the transmission paths
1
and
2
. The reflection of the distorted portions of the waveforms causes to further disturb the waveforms of the output signals Y
1
and Y
2
. Accordingly, signals having proper waveforms may not be transferred to their destinations. Further, if there are other transmission paths adjacent to the transmission paths
1
and
2
, wiring capacity between the transmission paths
1
and
2
and the adjacent transmission paths may cause so-called cross talk noise that the distortions of these waveforms cause noise to occur on other adjacent transmission paths.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a semiconductor integrated circuit that suppresses waveform distortions of output signals when logical levels of the output signals are changed in accordance with an input signal.
The semiconductor integrated circuit according to one aspect of this invention comprises a first MOS transistor of a first conductivity type having a drain terminal connected to a first node; a second MOS transistor of a second conductivity type different from the first conductivity type, having a drain terminal connected to said first node; a third MOS transistor of the first conductivity type having a drain terminal connected to a second node and a source terminal connected to a source terminal of said first MOS transistor; a fourth MOS transistor of the second conductivity type having a drain terminal connected to said second node and a source terminal connected to a source terminal of said second MOS transistor; and a driver circuit which generates first to fourth control signals whose logical levels change in response to a common input signal, and applies the signals to respective gate terminals of said first to fourth MOS transistors. In this structure, the first control signal starts to change from a low level to a high level at a first time in response to a first level change of the input signal from a high level to a low level, and starts to change from the high level to the low level at a second time in response to a second

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