Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-07-27

2002-11-05

Miska, Vit (Department: 2859)

Horology: time measuring systems or devices

Time interval

Electrical or electromechanical

C326S016000, C714S724000, C714S734000

Reexamination Certificate

active

06477115

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit (IC) having a complementary metal oxide film semiconductor element (CMOS) structure. More particularly, this invention relates to a semiconductor integrated circuit comprising a monitor circuit for evaluation used to determine characteristics of a manufacturing process of the semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
These days an IC tester is widely used to identify defective products during the production of CMOS-ICs, in order to produce ICs on a large scale and improve productivity. Various defective product identification (testing) methods are known that use the IC tester. For example, one method for evaluating the state of the transistor characteristics and interconnections (AL interconnections) is achieved by evaluating the operating speed of the IC. The operating speed of the IC should preferably be evaluated by testing the functions at the actual operating frequency of the IC being evaluated.
However, the present day ICs function at increasingly higher speeds and are highly integrated. Consequently, it has been extremely difficult to carry out a function test at the actual operating frequency due to the load when creating a test vector for the function test at the actual operating frequency (the level of difficulty in creating the vector, the time required to create the vector, etc.), and the ambiguity of the created test vector, and the like. Another method for testing this type of high-speed, highly-integrated IC is to measure the data signal transmission time (delay time) of a path comprising multiple gates within the IC.
This delay time is measured either by using a given path in the built-in logical circuit of the IC, or by providing a delay monitor circuit for evaluating the operating speed in the IC. This method measures the time taken for an input data signal to travel along the path or through the delay monitor circuit, evaluates the condition of the transistor characteristics and interconnections (AL interconnections) and thereby detects the defective products.
FIG. 19
shows a circuit constitution of a conventional delay monitor circuit.
This delay monitor circuit
50
is provided between an input circuit
51
, which is connected to a test terminal for data signal input IN, and an output circuit
52
, which is connected to a test terminal for data signal output OUT. The delay monitor circuit
50
comprises a delay circuit
54
which in turn comprises many delay elements
53
, such as inverters, connected in series. When measuring the delay using the delay monitor circuit
50
, a data signal for testing is input from the test terminal for data signal input IN. This data signal passes through the input circuit
51
, the delay circuit
54
, the output circuit
52
, and is output from the test terminal for data signal output OUT. The time taken for the data signal to travel from the input circuit
51
to the output circuit
52
is measured as the delay time.
FIG. 20
is a diagram showing a circuit constitution of another conventional delay monitor circuit. In addition to the delay monitor circuit
50
shown in
FIG. 19
, the delay monitor circuit
56
further comprises a NAND gate
55
provided between the input circuit
51
and the delay circuit
54
. A ring oscillator is formed by feeding back the last-stage output of the delay circuit
54
to one of the input terminals of the NAND gate
55
. In this delay monitor circuit
56
, the delay time is evaluated by measuring the oscillating frequency of the ring oscillator.
FIG. 21
is a diagram showing the chip arrangement of a conventional semiconductor integrated circuit (IC). This IC comprises a built-in logical circuit region
61
, an input buffer circuit region for test terminal
63
, an output buffer circuit region for test terminal
64
, input/output buffer circuit regions
66
other than the input buffer circuit region for test terminal
63
and the output buffer circuit region for test terminal
64
, and pads (PAD)
65
provided in each of the input/output buffer circuit regions.
In this IC, the input circuit
51
and output circuit
52
shown in FIG.
19
and
FIG. 20
are provided in the input buffer circuit region for test terminal
63
and in the output buffer circuit region for test terminal
64
respectively, and the delay monitor circuits
50
and
56
shown in FIG.
19
and
FIG. 20
are provided in the regions
62
of the built-in logical circuit region
61
. The delay time is evaluated using the delay monitor circuits
50
and
56
.
However, according to the conventional semiconductor integrated circuits using the delay monitor circuit
50
described above, the measured delay time also includes the delay times of the input and output circuits
51
and
52
. Consequently, there is a disadvantage that, since the effect of the delay times in the input and output circuits
51
and
52
must be taken into consideration, the precision of the evaluation of the semiconductor integrated circuit is reduced. Furthermore, according to the conventional semiconductor integrated circuit using the delay monitor circuit
56
(ring oscillator) described above, since the delay time is evaluated by measuring the oscillating frequency, it is only possible to measure the average operating speeds of all the P-channel transistor and the N-channel transistor present inside all the delay elements. That is, since it is not possible to separately monitor the P-channel transistors and the N-channel transistors, there is a disadvantage that detailed process characteristics cannot be evaluated.
Furthermore, according to the conventional semiconductor integrated circuit which uses the delay monitor circuit
50
and the semiconductor integrated circuit which uses the delay monitor circuit
56
(ring oscillator) described above, since the delay monitor circuits are provided in built-in logical circuit regions of the IC, the design region of the built-in logical circuit is reduced, resulting in disadvantages of increased limitations on providing interconnections, and increased costs. Furthermore, since the elements forming the delay monitor circuits are arranged unevenly in the built-in logical circuit regions of the IC, the effect of the transistor characteristics and the interconnections on the speed become unclear. Resultantly, the precision of the evaluation of the semiconductor integrated circuit is reduced.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a semiconductor integrated circuit which can be evaluated at high precision and in great detail, and wherein the design region of a built-in logical circuit can be reduced, and costs can be lowered without increasing restrictions on the arrangement of the interconnections.
In order to solve the above problems and achieve the objects, the semiconductor integrated circuit according to this invention comprises a monitor circuit for evaluation on a semiconductor substrate, the monitor circuit being provided in an input/output buffer circuit region of the semiconductor integrated circuit. This monitor circuit comprises a delay circuit, a first flip-flop circuit, and a second flip-flop circuit. The first and second flip-flop circuits are connected to an input stage and an output stage of the delay circuit respectively. Because of such a structure, the P-channel transistors and the N-channel transistors can be individually monitored without being affected by the delay of the input/output circuits, and the monitor circuit need not be provided in the built-in logical circuit region.
Further, many and different types of monitor circuits are provided, and each type of monitor circuit has a different type of delay circuit. Thus, since each of the multiple monitor circuits of multiple types has a different type of delay circuit, a single semiconductor integrated circuit can be evaluated using a variety of delay circuits.
Further, the monitor circuit is provided in a ring around the top face of the semiconductor substrate. Therefore, it is possible to form

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