Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-04-23

2002-10-08

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230080, C365S233100

Reexamination Certificate

active

06462993

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having memory cells. In particular, the present invention relates to a semiconductor integrated circuit having a redundancy circuit for relieving a defect in a memory cell or a defect in a peripheral circuit thereof.
2. Description of the Related Art
In general, semiconductor integrated circuits such as a DRAM have redundancy circuits so that lattice defects in their substrates and other defects resulting from particles produced in fabrication processes are relieved for an improved yield.
FIG. 1
shows the essential parts of a DRAM that has a redundancy circuit of this type. In the diagram, thick lines represent signal lines including a plurality of lines each.
The DRAM has an input circuit
2
, a command decoder
4
, an input buffer
6
for receiving a clock signal CLK, an address input circuit
8
for receiving an address signal ADD, a latching circuit
10
, a predecoder
12
, a column decoder
14
, a fuse circuit
16
, a redundancy judgement circuit
18
, a redundancy predecoder
20
, and a redundancy column decoder
22
. The predecoder
12
, column decoder
14
, fuse circuit
16
, redundancy judgement circuit
18
, redundancy predecoder
20
, and redundancy column decode
22
are circuits that operate in response to a supply of a column address. That is, this DRAM has a redundancy circuit for relieving a defect associated with a column address.
The input circuit
2
has an input buffer
2
a
for receiving command signals /CS, /RAS, /CAS, and /WE (hereinafter, these signals are collectively referred to as a command signal CMD), and a latch
2
b
for accepting the received signals in synchronization with an internal clock signal CLKINZ which is output from the input buffer
6
. The command decoder
4
decodes the accepted command signal, and outputs command signals ACTV, READ, and WRITE, as well as an RAS address latching signal ERALPZ and a CAS address latching signal EXTPZ, depending on the decoding result.
The address input circuit
8
has an input buffer
8
a
for receiving the address signal ADD, and a latch
8
b
for accepting the received signal in synchronization with the internal clock signal CLKINZ. The latch
8
b
outputs the accepted signal as an internal address signal ADDIN. Incidentally, the DRAM of this example employs an address multiplex method, in which a row address or a column address is supplied to the DRAM as the address signal ADD.
The latching circuit
10
has a row latch
10
a
and a column latch
10
b.
The row latch
10
a
accepts a row address in synchronization with the RAS address latching signal ERALPZ, and outputs the accepted signal as a row address signal RADD. The row address signal RADD is supplied to not shown circuits associated with row addresses. The column latch
10
b
accepts a column address in synchronization with the CAS address latching signal EXTPZ, and outputs the accepted signal as a column address signal CADD.
The predecoder
12
accepts, when a redundancy judgement signal RDN is inactivated (at low level), the column address signal CADD in synchronization with a column enable pulse CEP which is generated by a not-shown control circuit. The predecoder
12
decodes the accepted signal to output a predetermined predecoding signal PDEC. The column decoder
14
decodes the predecoding signal PDEC, and activates a predetermined column line selecting signal CL.
The fuse circuit
16
includes a plurality of fuses formed of polysilicon or the like, and a control circuit thereof. The fuses are blown depending on a defect address (column address) found in a probe test under a wafer state. The fuse circuit
16
outputs the defect address set by the fuse blowing, as a redundancy column address signal RCADD. The redundancy judgement circuit
18
compares the column address signal CADD and the redundancy column address signal RCADD, and if these signals coincide with each other, activates (to high level) the redundancy judgement signal RDN.
The redundancy predecoder
20
accepts the redundancy judgement signal RDN in synchronization with the column enable pulse CEP, and outputs the accepted signal as a redundancy predecoding signal RPDEC. The redundancy column decoder
22
receives the redundancy predecoding signal RPDEC, and activates a redundancy column line selecting signal RCL The redundancy column line selecting signal RCL is activated when the comparison between the address signals CADD and RCADD in the redundancy judgement circuit
18
shows a coincidence. Then, the redundancy circuit operates to perform a read operation or a write operation on a not shown redundancy memory cell.
FIG. 2
shows an example of read operations by the DRAM shown in FIG.
1
.
For a start, the command signal CMD (active command ACTV) and the address signal ADD (row address R
1
) are supplied to the DRAM in synchronization with the clock signal CLK. The latch
2
b
shown in
FIG. 1
accepts the command signal CMD in synchronization with the internal clock signal CLKINZ (FIG.
2
(
a
)). The latch
8
b
accepts the row address R
1
in synchronization with the internal clock signal CLKINZ, and outputs the accepted address as the internal address signal ADDIN (FIG.
2
(
b
)). Thereafter, a word line (not shown) corresponding to the row address R
1
is selected.
In synchronization with the next clock signal CLK, the command signal CMD (read command READ) and the address signal ADD (column address C
1
) are supplied to the DRAM. Here, the column address C
1
is an address corresponding to the location where a defect lies. Its information is written in the fuse circuit
16
. The latch
8
b
accepts the column address C
1
in synchronization with the internal clock signal CLKINZ, and outputs the accepted address as the internal address signal ADDIN (FIG.
2
(
c
)).
The command decoder
4
receives the read command READ, and then turns the CAS address latching signal EXTPZ to high level after a predetermined period of time. The latch
10
b
accepts the column address C
1
in synchronization with the rising edge of the CAS address latching signal EXTPZ, and outputs the accepted address as the column address signal CADD (FIG.
2
(
d
)). The column address signal CADD is supplied to the predecoder
12
and the redundancy judgement circuit
18
. The column address signal CADD (column address C
1
) coincides with the redundancy column address signal RCADD from the fuse circuit
16
. Thus, the redundancy judgement circuit
18
turns the redundancy judgement signal RDN to high level (FIG.
2
(
e
)). Here, the time T
1
that elapses from the change of the column address signal CADD to the activation of the redundancy judgement signal RDN is the period necessary for the redundancy judgement circuit
18
to perform the redundancy judgement.
The activation of the redundancy judgement signal RDN inactivates the predecoder
12
. The inactivation of the predecoder
12
disables operations on the normal memory cell corresponding to the column address C
1
. The redundancy predecoder
20
accepts the redundancy judgement signal RDN in synchronization with the rising edge of the column enable pulse CEP, and outputs the redundancy predecoding signal RPDEC (FIG.
2
(
f
)). The redundancy column decoder
22
receives the redundancy predecoding signal RPDEC, and activates (to high level) the redundancy column line selecting signal RCL (FIG.
2
(
g
)). The activation of the redundancy column line selecting signal RCL brings into conduction a column switch that is formed as the redundancy circuit. Thereby, data read from the redundancy memory cell (not shown) is output.
In synchronization with the next clock signal CLK, the command signal CMD (read command READ) and the address signal ADD (column address C
2
) are supplied to the DRAM. Here, the column address C
2
is not an address corresponding to the defective portion. Therefore, the redundancy judgement circuit
18
turns the redundancy judgement signal RDN to low level (FIG.
2
(
h
)).
The predecoder
12
is acti

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