Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-12-28

2002-08-20

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S220000, C365S221000, C365S239000, C365S240000, C365S189120

Reexamination Certificate

active

06438054

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which transmits data in serial to/from the exterior and reads/writes data in parallel from/to memory cells. In particular, the present invention relates to a technology of converting data at high speed.
2. Description of the Related Art
SDRAMs (Synchronous DRAMs) are known as a semiconductor integrated circuit operating their input/output interfaces at high speed in synchronization with a clock signal or the like to input/output data at high speed. Their transmitting data in serial to/from the exterior and reading/writing data in parallel from/to memory cells improve its data transmission speed.
FIG. 1
shows the outlines of an output interface unit in the SDRAM of this type.
An output interface unit
1
comprises a data selector
2
, a parallel-serial converter
3
, a shift register
4
, and a data output buffer
5
. This output interface unit
1
except the shift register
4
is formed for each of a plurality of data input/output terminals DQ.
The data selector
2
comprises four switches
2
a
consisting of CMOS transmission gates or the like. Each of the switches
2
a
receives data signals DB
0
-DB
3
output from not-shown memory cells, and outputs one of the received signals as a data signal DBS
0
(DBS
1
, DBS
2
, or DBS
3
) in accordance with address signals AD
0
and AD
1
. In this diagram, the data selector
2
is shown connecting its switches when the address signals AD
0
and AD
1
are “10” in binary.
The parallel-serial converter
3
comprises four switches
3
a
each consisting of CMOS transmission gates or the like. The switches
3
a
are turned on upon the activation of connecting signals NA, NB, NC, and ND, and respectively transmit the data signals DBS
0
-DBS
3
as a data output signal DOUT.
The shift register
4
performs shift operations in synchronization with a clock signal CLK, activating the connecting signals NA, NB, NC, and ND in this order.
The data output buffer
5
outputs serial read data transmitted as the data output signal DOUT to the data input/output terminal DQ.
In this SDRAM, the order of outputting the data signals DBS
0
-DBS
3
in a read operation is determined in accordance with lower address signals AD
0
and AD
1
supplied from the exterior. Such an operating mode that data read from memory cells in parallel are successively output is generally referred to as a burst output mode.
FIG. 2
shows an example of the read operations by the SDRAM described above.
Initially, the SDRAM accepts a read command READ
1
and address signals in synchronization with the CLK signal on the cycle
1
to start a read operation. In this example, the address signals AD
0
and AD
1
supplied along with the read command READ
1
are “10” in binary.
The data selector
2
shown in
FIG. 1
receives the address signals AD
0
and AD
1
, and connects the switches
2
a.
The data signals DB
0
, DB
1
, DB
2
, and DB
3
read from memory cells are transmitted as the data signals DBS
2
, DBS
3
, DBS
0
, and DBS
1
, respectively, through the data selector
2
.
The shift register
4
activates the connecting signals NA, NB, NC, and ND in synchronization with the clock signal CLK on the cycles
3
,
4
,
5
, and
6
, respectively.
The switches
3
a
in the parallel-serial converter
3
receive the connecting signals NA, NB, NC, and ND, and sequentially output the data signals DBS
2
, DBS
3
, DBS
0
, and DBS
1
as the data output signal DOUT.
Then, the data output signal DOUT of serial form is output to the data input/output terminal DQ via the data output buffer
5
. That is, when the address signals AD
0
and AD
1
are “10,” the data signals are output in the order of DB
2
, DB
3
, DB
0
, and DB
1
(4-bit burst output).
In synchronization with the clock signal CLK on the cycle
5
, the SDRAM also accepts the next read command READ
2
and address signals AD
0
and AD (“00” in binary).
The data selector
2
switches over the individual switches
2
a
according to the address signals AD
0
and AD
1
. Then, the data signals DB
0
, DB
1
, DB
2
, and DB
3
read from memory cells are respectively transmitted as the data signals DBS
0
, DBS
1
, DBS
2
, and DBS
3
through the date selector
2
. In synchronization with the connecting signals NA, NB, NC, and ND sequentially activated, the parallel-serial converter
3
outputs the data signals DBS
0
, DBS
1
, DBS
2
, and DBS
3
as the serial data output signal DOUT.
Then, the serial data output signal DOUT is output to the data input/output terminal DQ via the data output buffer
5
. That is, when the address signals AD
0
and AD
1
are “00,” the data signals are output in the order of DB
0
, DB
1
, DB
2
, and DB
3
.
On the next read command READ
3
, the read data are output to the data input/output terminal DQ in the order of the data signals DB
3
, DB
0
, DB
1
, and DB
2
in accordance with the address signals AD
0
and AD
1
(“11” in binary).
In the output interface unit
1
described above, the data signals DB
0
-DB
3
are output to the exterior controlled by both the data selector
2
and the parallel-serial converter
3
. Therefore, it is required to consider the timing margins of both the data selector
2
and the parallel-serial converter
3
in the timing design of the SDRAM.
In addition, the data signals DB
0
-DB
3
are output to the exterior through the two switches
2
a
and
3
a
and this delays the outputs of the data signals by the propagation delay times of the switches
2
a
and
3
a.
As described above, in conventional SDRAMs, the output interface unit
1
has caused the data transmission speed of read data from memory cells to lower. SDRAMs are essentially characterized by operating their input/output interfaces at high speed. On this account, the output interface unit
1
needs to transmit read data from memory cells as fast as possible.
SUMMARY OF THE INVENTION
An object of the present invention is to transmit read data from memory cells at high speed.
Another object of the present invention is to perform a read operation at high speed in a semiconductor integrated circuit having memory cells.
Another object of the present invention is to perform a read operation at high speed in semiconductor integrated circuit having memory cells of a clock-synchronous type.
Another object of the present invention is to control the parallel-to-serial conversion of read data with a simple circuit.
Another object of the present invention is to perform a write operation at high speed in a semiconductor integrated circuit having memory cells.
According to one of the aspects of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches selected in a predetermined order. The switch control circuit controls the order of selecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order.
This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells.
According to another aspect of the semiconductor integrated circuit in the present invention, the serial data converted by the parallel-serial converter are output to the exterior through an output circuit. This can further heighten the speed of read operations, for example, in a semiconductor integrated circuit having a burst output function.
According to another aspect of the semiconductor integrated circuit in the present invention, each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior. This can heighten the spee

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