Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-07-10
2002-12-31
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S096000, C326S098000, C327S530000, C327S538000, C327S543000, C365S226000, C365S233100
Reexamination Certificate
active
06501300
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit, and particularly to a technology for electrically cutting off a logic circuit unit from operating power supplies therefor upon standby and reducing a leak current developed upon standby. The present invention relates to a technology effective for application to, for example, a battery-driven cellular phone or PAD (Personal Digital Assistant) or the like.
BACKGROUND ART
With technical advances in semiconductor integrated circuit and the wide range of its application field, a reduction in power consumption of the semiconductor integrated circuit (semiconductor chip) has become important in recent years. Namely, the reduction in power consumption of the semiconductor integrated circuit has come to be an important consideration in battery-driven applications such as a PDA, etc., in maximizing operating time. Reducing the power-supply or source voltage is most effective for the reduction in power consumption. However, as side effects may be mentioned, a reduction in current supply capability of each transistor, and a reduction in working speed of the transistor can result. In order to overcome such a problem, there is known a method of reducing Vth (threshold voltage) of the transistor. However, the mere reduction in threshold voltage will increase the leak current developed when the transistor is held in an off state. In doing so, needless current consumption will increase even when the semiconductor integrated circuit is brought to a standby state. The standby state is a so-called one low power consumption mode capable of stopping the supply of a clock signal for synchronous operation, for example and achieving its state. A technology that has been proposed to overcome such a problem is the MT-CMOS (Multi-Threshold CMOS). The present technology has been described in, for example, “Electronic Technology” issued by THE NIKKAN GOGYO SHINBUN, LTD., p.29-32, September 1994.
The MT-CMOS technology utilizes transistors (high threshold voltage transistors) each having a large threshold voltage ranging from about 0.5V to about 0.7V and transistors (low threshold transistors) each having a small threshold voltage ranging from about 0.2V to about 0.3V when an operating power supply is about 1V, for example. Low threshold voltage transistors are used for logic gates constituting a logic circuit group. Operating power supplies for the respective logic gates are supplied from source or power-supply terminals through MOS transistors for power supply, which comprise the high threshold voltage transistors. When the MOS transistors are turned on to supply the operating power supplies to each individual logic gate, the low threshold voltage MOS transistors constituting the logic gates can be operated at high speed because of their low threshold voltages. When the MOS transistors are turned off upon standby, a leak current that will flow through a turnedoff transistor of each logic gate, can be cut off because of the high threshold voltage of each MOS transistor for power supply.
It has been revealed by the present inventors that in the MT-CMOS technology, the leak current developed upon standby can be reduced, whereas the leak current developed upon operation cannot be reduced in spite of the operating clock frequency.
Namely, most personal digital assistants respectively have an operation mode between a high-speed operation mode high at the clock signal frequency and a standby mode for stopping a clock signal, i.e., a low-speed operation mode operated at a low-speed clock signal frequency. During a waiting operation of a cellular phone, for example, call detection and an outgoing or dialing operation for notifying the present position may be carried out at predetermined intervals, and less throughput is provided as compared with signal processing or the like made while a call is in progress. Thus, such a waiting process will be enough if the phone is operated in synchronism with a low-speed clock signal.
A circuit operated in synchronism with the clock signal performs a logic operation for each clock signal cycle and carries out the operation of latching the result thereof in a signal transmission system. If the clock signal becomes slow, then the logic operation is determined by some of the clock cycle, and the circuit is kept at a constant state during the remaining period. At this time, each turned-off transistor continues to have a flow of leak current if the threshold voltage thereof is small. The MT-CMOS technology is accompanied by a problem that since the high threshold voltage MOS transistors for supplying power remain at the on state except for during the standby state, the leak current relatively increased when the frequency of the operating clock signal for each logic gate is low, cannot be reduced.
An object of the present invention is to reduce the leak current developed when a transistor is held in an off state.
Another object of the present invention is to provide a data processor with a semiconductor integrated circuit capable of reducing the leak current developed in a turned-off transistor when the frequency of the operating clock signal is low, in other words, when a logic circuit block is operated at low speed.
A further object of the present invention is to provide a data processor with a semiconductor integrated circuit wherein operating power supplies are supplied to within each of the logic circuit blocks through a switch transistor whose threshold voltage is rendered high as compared with each transistor lying in the logic circuit block, and a leak current flowing through each turned-off transistor lying within the logic circuit block can be reduced.
The above and other objects, and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
DISCLOSURE OF THE INVENTION
The present invention includes a logic circuit block operated in synchronism with a clock signal, at least one power supply switch which supplies power to the logic circuit block, and a switch control circuit which controls the power supply switch. The switch control circuit switch-controls the power supply switch so as to bring a period shorter than the cycle of the clock signal to the on operation period in synchronism with the clock signal. As an example, using the above, the logic circuit block is activated in synchronism with a first operating clock signal having a frequency lower than that of a second operating clock signal for defining the maximum operation speed of the logic circuit block. At this time, the logic circuit block does not develop a malfunction in the logic operation itself theoretically if capable of operation for each cycle of the first operating clock signal at least only for a predetermined time defined by the frequency of the second operating clock signal, for example, a one-cycle period. This is because the logic block is designed so as to operate based on the second operating clock signal. Thus, since the supply of operating power to the logic circuit block is cut off except for a period necessary for a circuit operation, a leak current that will flow through each turned-off transistor in the logic circuit block in the meantime, can be significantly reduced.
If consideration is given to points about a high-speed operation of the logic circuit block with respect to reductions in the operating power supplies and a reduction in leak current at standby in a manner similar to the MT-CMOS technology at this time, then threshold voltages of transistors constituting the logic circuit block can be rendered relatively small to allow the high-speed operation upon a low-voltage operation. Further, the threshold voltage of a current supply switch can be rendered relatively large to reduce the leak current at standby.
When the above means of the present invention is compared with the MT-CMOS technology, the present invention can reduce the leak current developed when the transistors of the logic circuit block are turne
LandOfFree
Semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2932483