Electronic digital logic circuitry – Reliability
Reexamination Certificate
2001-04-09
2002-07-16
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Reliability
C326S010000, C326S014000
Reexamination Certificate
active
06420896
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test circuit and a redundancy circuit for a storing circuit section of a semiconductor integrated circuit device.
2. Description of the Background Art
For example, Japanese Patent Application Laid-Open No. 8-94718 (1996) (U.S. Pat. No. 5,815,512) has disclosed a conventional test circuit and redundancy circuit for a storing circuit section of a semiconductor integrated circuit device.
FIGS. 71
to
74
are diagrams showing a conventional semiconductor integrated circuit constituted by an RAM comprising a test circuit and a redundancy circuit.
FIG. 71
is a diagram showing a positional relationship between
FIGS. 72 and 73
, and
FIGS. 72 and 73
are circuit diagrams showing a circuit structure of a conventional RAM.
FIG. 74
is a circuit diagram showing an internal structure of each of scan flip-flops SFFC <i> to SFFC <i+4> having comparing circuits illustrated in
FIGS. 72 and 73
.
As shown in
FIG. 74
, a comparator
201
is constituted by an EX-OR gate
202
and an NAND gate
203
. The EX-OR gate
202
receives input data D and expectation data EXP at one of inputs and the other input respectively, and the NAND gate
203
has one of inputs connected to an output of the EX-OR gate
202
and receives a comparison control signal CMP at the other input. An output of the NAND gate
203
is sent as an output of the comparator
201
.
An AND gate
204
has one of inputs connected to the output of the comparator
201
, and a selector
205
has a “0” input for receiving a serial input (data) SI, a “1” input connected to an output of the AND gate
204
and a control input for receiving a test mode signal TM. Then, the selector
205
outputs, from an output section Y, a signal obtained from the “1” input/“0” input based on “1”/“0” of the test mode signal TM.
A selector
206
has a “0” input for receiving the input data D, a “1” input connected to the output section Y of the selector
205
and a control input for receiving a shift mode signal SM. Then, the selector
206
outputs, from the output section Y, a signal obtained from the “1” input/“0” input based on “1”/“0” of the shift mode signal SM. A signal obtained from the output section Y of the selector
206
is sent as output data P.
A D-FF (D flip-flop)
207
has a D input to which the output section Y of the selector
206
is connected, and receives a timing signal (clock signal) T at a toggle input T. A signal obtained from a Q output section is output as a data output Q and a serial output (data) SO to the outside and is fed back to the other input of the AND gate
204
.
As shown in
FIGS. 72 and 73
, five scan flip-flops SFFC <i> to SFFC <i+4> having a circuit structure shown in
FIG. 74
are connected in series to have a scan path for an RAM test. In some cases, the scan flip-flop SFFC < > will be hereinafter referred to as an SFFC < >.
More specifically, the SFFC <i+4> receives serial input data SIDO <i+4> as a serial input SI and has a serial output SO connected to a serial input SI of the SFFC <i+2>. Similarly, the SFFC <i+2>, the SFFC <i+1> and the SFFC <i> are connected in series, and the serial output SO of the SFFC <i> in a last stage is output as serial output data SODO <i>.
The SFFC <i> to the SFFC <i+4> receive a shift mode signal SM, a test mode signal TM, a comparison control signal CMP and a timing control signal CKDO in common (the timing control signal CKDO is input as the timing signal T), and receive data outputs DO <i> to DO <i+4> of an RAM
211
as respective input data D of the SFFC <i> to SFFC <i+4>. Respective data outputs P of the SFFC <i> to the SFFC <i+3> are sent as data outputs P <i> to P <i+3>.
Moreover, the SFFCs <i>, <i+2> and <i+4> receive expectation data EXPA as the expectation data EXP, and the SFFCs <i+1> and <i+3> receive expectation data EXPB as the expectation data EXP. In other words, an expectation of a comparing operation can be set to include even and odd bits having different values.
Selectors
230
to
233
constituting a redundancy-relieved output selecting circuit receive the data outputs DO <i> to DO <i+3> at respective “0” inputs, receive data outputs DO <i+1> to DO <i+4> at respective “1” inputs, and receive output data F <i+1> to F <i+4> at respective control inputs. Then, outputs of the selectors
230
to
233
constituting a redundancy-relieved input selecting circuit are sent as redundancy-relieved data outputs XDO <i> to XDO <i+3>.
Each of AND gates
221
to
223
receives each of serial outputs SO <i+1> to SO <i+3> at one of inputs. The AND gate
221
receives an output of the AND gate
222
at the other input, the AND gate
222
receives an output of the AND gate
223
at the other input, and the AND gate
223
receives a serial output SO <i+4> at the other input. Then, the outputs of the AND gates
221
to
223
are sent as the output data F <i+1> to F <i+2> and the serial output SO <i+4> is sent as the output data F <i+4>.
On the other hand, an OR gate
215
receives a redundancy-relieved data input XDI <i> at one of inputs, and receives the output data F <i+1> at the other input. Selectors
234
to
236
receive redundancy-relieved data inputs XDI <i+1> to XDI <i+3> at respective “0” inputs, receive the redundancy-relieved data inputs XDI <i> to XDI <i+2> at respective “1” inputs, and receive the output data F <i+2> to F <i+4> at respective control inputs. The selectors
230
to
236
output the signals to be received at the “0”/“1” inputs based on “0”/“1” of the signal received at the control inputs. Moreover, the OR gate
215
does not need to be essential.
Then, a scan path circuit DISCAN inputs an output of the OR gate
215
as input data XI <i>, the outputs of the selectors
234
to
236
as input data XI <i+1> to <i+3>, and a redundancy-relieved data input XDI <i+4> as input data XI <i+4>.
The scan path circuit DISCAN receives a control signal CTRL including serial input data SIDI <i+4> and outputs serial output data SIDO <i>, and outputs input data DI <i> to DI <i+4> to a 5-bit input section for the input data DI <i> to DI <i+4> of the RAM
211
.
FIG. 75
is a circuit diagram showing an internal structure of the scan path circuit DISCAN. As shown in
FIG. 75
, scan flip-flops SFFDI <i> to SFFDI <i+4> are connected in series. In some cases, the scan flip-flop SFFDI < > will be hereinafter referred to as an SFFDI < >.
FIG. 76
is a circuit diagram showing an internal structure of the scan flip-flop SFFDI < > illustrated in FIG.
75
. As shown in
FIG. 76
, the SFFDI < > is constituted by a selector
241
and a D-FF
242
, and the selector
241
receives input data D at a “0” input, receives a serial input SI at a “1” input and receives a shift mode signal SM at a control input. A signal obtained from an output section Y of the selector
241
is given to a D input of the D-FF
242
and is output as a data output P. The D-FF
242
receives a timing signal T at a toggle input T and sends a data output Q and a serial output SO from a Q output.
Returning to
FIG. 75
, the SFFDI < > is sequentially connected in series in order of the SFFDI <i+4> to the SFFDI <i>, and the SFFDI <i+4> receives the serial input data SIDI <i+4> as a serial input SI and the SFFDI <i> outputs serial output data SIDO <i> as a serial output SO.
Shift mode input data SMDI are input as the shift mode signal SM of the SFFDI <i>
Mitsubishi Denki & Kabushiki Kaisha
Tokar Michael
Tran Anh Q.
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