Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-12-29

2002-07-09

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S190000, C365S230030

Reexamination Certificate

active

06418072

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a function of data compressing test hat efficiently executes a read/write operation test by compressing data signals.
2. Description of the Related Art
The memory capacity of memory LSI such as DRAM (Dynamic Random Access Memory) has been increasing every year. Because of the increase of the memory capacity, the address spaces of these memory LSI can be sufficiently secured even in the case where the input/output terminals are 16 bits or 32 bits (in general, referred to as plural bits products). For example, a work memory that is used for a 32-bit microcomputer can be constructed using a single 32-bit memory LSI.
On the other hand, as the number of external terminals increases, the number of memory LSI that can be mounted on a test-use evaluation board tends to decrease. The efficiency of testing the memory LSI depends on the number of the input/output terminals of an LSI tester. For example, if the number of the input/output channels of an LSI tester is 256, 32 of DRAMs each having 8-bit input/output terminals can simultaneously are tested; however, only eight of DRAMs each having 32-bit input/output terminals can simultaneously be tested. As a result, the testing cost (especially testing for shipment) significantly increases.
Recently, to prevent the increase of the testing cost due to the increase of the input/output terminals, a memory LSI that has a data compression function of efficiently executing the read/write operation test by compressing data signals within the memory LSI has been developed.
FIG. 1
shows a memory core
10
of an SDRAM (Synchronous DRAM) having the data compressing function. This SDRAM has 32-bit input/output terminals. Each bit of the input/output data transmitted through input/output terminals also is referred to as DQ hereafter.
The memory core
10
has ninety-six memory cell arrays
12
(memory cell regions) that are arranged in eight rows in the vertical direction and in twelve columns in the horizontal direction in the figure.
One row of the memory cell arrays
12
is assigned one of blocks BLK
0
to BLK
7
. The blocks BLK
0
, BLK
4
, blocks BLK
1
, BLK
5
, blocks BLK
2
, BLK
6
, and blocks BLK
3
, BLK
7
, respectively, are activated at the same time. The twelve memory cell arrays
12
that are constructed of four rows × three columns (reference characters A to H in the figure) correspond to predetermined DQs. The memory cells assigned character A correspond to DQ
0
, DQ
1
, DQ
14
, and DQ
15
. The memory cells assigned character B correspond to DQ
2
, DQ
3
, DQ
12
, and DQ
13
. The memory cells assigned character C correspond to DQ
4
, DQ
5
, DQ
10
, and DQ
11
. The memory cells assigned character D correspond to DQ
6
, DQ
7
, DQ
8
, and DQ
9
. The memory cells assigned character E correspond to DQ
18
, DQ
19
, DQ
28
, and DQ
29
. The memory cells assigned character F correspond to DQ
16
, DQ
17
, DQ
30
, and DQ
31
. The memory cells assigned character G correspond to DQ
22
, DQ
23
, DQ
24
, and DQ
25
. The memory cells assigned character H correspond to DQ
20
, DQ
21
, DQ
26
, and DQ
27
. Regions of memory cell arrays assigned characters A to H, each of which is constructed of twelve memory cell arrays
12
, will be also referred to as groups A to H, respectively, hereafter.
Outside each of the groups B, D, F, and H, a column decoder
14
is arranged. A row decoder
16
is arranged between groups C, D and groups E, F. Word lines WL are wired to extend from the row decoder
16
towards the memory cell arrays
12
at both sides in the horizontal direction.
Between the memory cell arrays
12
, a plurality of main data line pairs MDLP is wired along the vertical direction of the figure, and a plurality of sub data line pairs SDLP is wired along the horizontal direction. The sub data line pairs SDLP are connected to the main data line pairs MDLP by data line switches
18
indicated by black dots. That is, the data lines have a hierarchical structure. The groups A, B, the groups C, D, the groups E, F, and the groups G, H have the same structure (including mirror symmetry), respectively, except for the DQ numbers. Because of this, groups A, B are mainly explained hereinafter.
FIG. 2
shows the detailed layout of the groups A, B.
For each memory cell array
12
, a plurality of bit line pairs BLP is wired along the vertical direction of the figure. In order to avoid interference, each bit line pair BLP is wired between bit line pairs BLP of other bit numbers. The bit line pairs BLP are connected to the sub data line pairs SDLP by column line switches
20
, which are indicated by outline dots. The bit line pairs BLP, which are connected to a column line switch
20
formed between particular blocks (between BLK
1
and BLK
2
, for example), are wired into the respective blocks (BLK
1
and BLK
2
). The bit line pairs BLP that are connected to the column line switch
20
formed outside the blocks BLK
0
, BLK
3
are wired into the blocks BLK
0
, BLK
3
, respectively.
The arrows indicated by thick lines in the figure show the data flows of the read operation and write operation. For example, the data to be read from a memory cell array
12
in the block BLK
1
of the group B is transmitted to the exterior of group B through bit line pair BLP, column line switch
20
, sub data line pair SDLP, data line switch
18
, and main data line pair MDLP (
FIG. 2
(i)). The data to be written to memory cell array
12
in the block BLK
4
(group A) is transmitted from the exterior to a memory cell (not shown in the figure) through main data line pair MDLP, data line switch
18
, sub data line pairs SDLP, column line switch
20
, and bit line pair BLP (
FIG. 2
(ii)).
Each block (for example, BLK
0
constructed of groups B, D, F, H shown in
FIG. 1
) has two word line relief circuits
22
. The word line relief circuit
22
has a redundancy word line (not shown in the figure) and a plurality of redundancy memory cells (not shown in the figure) connected to the redundancy word line. Using the word line relief circuits
22
, the blocks BLK
0
to BLK
7
each can relieve two word line defects or two bit defects.
Each of groups A to H has at least one bit line relief circuit
24
. The bit line relief circuit
24
has a redundancy bit line pair (not shown in the figure), and a plurality of redundancy memory cells (not shown in the figure) connected to the redundancy bit line pair. Using the bit line relief circuit
24
, the groups A to H each can relieve one bit line defect or one bit defect.
FIG. 3
shows a control circuit
26
formed between the blocks BLK
0
and BLK
1
.
Bit line pairs BLP of the blocks BLK
0
, BLK
1
are connected to a shared bit line pair SHBLP through bit line switches
28
, which consist of an nMOS transistor. The bit line switches
28
are controlled by control signals BT
0
, BT
1
, respectively, which are activated in accordance with the column address. A sense amplifier
30
and a precharge circuit
32
are connected to the shared bit line pair SHBLP. When equalizing signal BRS is at the high level, the precharge circuit
32
supplies precharge voltage VPR to the shared bit line pair SHBLP and to the bit line pairs BLP that are connected to the shared bit line pair SHBLP by the control signals BT
0
, BT
1
. The sense amplifier
30
and precharge circuit
32
are shared by the blocks BLK
0
and BLK
1
through the bit line switches
28
. The shared bit line pair SHBLP is connected to the sub data line pair SDLP through column switch
20
consisting of nMOS transistors. The gate of the column switch
20
is controlled by a column line selecting signal CL, which is activated in accordance with the column address. A data line switch
18
, which connects the sub data line pair SDLP to the main data line pair MDLP, is constructed of nMOS transistors and an inverter. The gates of the data line switch
18
are controlled by a precharge signal BRS through the inverter. For example, the read operation of the block BLK
0
is exec

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