Semiconductor integrated circuit

Static information storage and retrieval – Read/write circuit – Bad bit

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3652257, 36523006, G11C 700

Patent

active

055089631

ABSTRACT:
N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.

REFERENCES:
patent: 4376300 (1983-03-01), Tsang
patent: 4471472 (1984-09-01), Young
patent: 4951253 (1990-08-01), Sahara et al.
patent: 5206831 (1993-04-01), Wakamatsu
K. Sasaki et al., "A 9ns 1 Mb CMOS SRAM", ISSCC Digest of Technical Papers, pp. 34-35 (1989).
M. Miyauchi et al., "4Mb Field Memory", ICD90-112, pp. 45-49 (1990).
H. Kikukawa et al., "Novel Flexible Redundancy Architecture for 64Mb DRAM and Beyond", IEICE Digest of Technical Papers of Autumn Conference, vol. 5, p. 152 (1992).

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