Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-06-22
2002-09-03
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S219000
Reexamination Certificate
active
06445627
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit technique and further a technique of making setting in each circuit block changeable. For example, the invention relates to a technique effective for application to a method of repairing a defective bit in a memory, adjustment of an operation timing of a memory, and a diagnosis test on the memory in a semiconductor integrated circuit having therein a plurality of memories.
BACKGROUND OF THE INVENTION
Conventionally, in a semiconductor integrated circuit having therein a semiconductor memory such as a RAM (Random Access Memory) or a memory, to improve the yield by repairing a defective bit included in the memory, a redundancy circuit including an address setting circuit for storing a spare memory column, a spare memory row, and a defective address is provided. A defective address is set in the redundancy circuit generally by a method using a fuse which can be programmed by a laser or the like. Examples of known techniques are Japanese Unexamined Patent Publication Nos. 274096/1992 (corresponding to U.S. Pat. Nos. 5,430,679) and 275494/1998 (corresponding to U.S. Pat. No. 5,859,801).
As the packing density of a semiconductor integrated circuit increases in recent years, an LSI having therein a plurality of memories on a single semiconductor chip is seen more often. For example, in some cases, in a processor for a computer, to provide various RAMs for a primary cache of a large capacity, a secondary cache, TLB, tag cache, memory for branch prediction, and write buffer, nearly 100 built-in RAMs are provided.
SUMMARY OF THE INVENTION
In the case of providing an LSI having therein a number of RAMs (memories) as described above with a redundancy circuit including an address setting circuit for storing a defective address for each built-in RAM, for example, when the number of built-in RAMs is 100 and a repair address consists of 10 bits, about 1,000 fuses are necessary. Consequently, a problem such that the chip size increases due to the redundancy circuit occurs.
The present inventors have found the following. In an LSI having therein about 100 RAMs each having a storage capacity of 1 Mbit or less, the probability that defective bits which can be repaired occur in all the 100 built-in RAMs is very low. Defective bits which can be repaired occur in a few to tens of built-in RAMs in many cases. Even if the redundancy circuits are provided for all the built-in RAMs, the yield cannot be improved so efficiently by the arrangement. It is also important to rationally diagnose a number of RAMs.
An object of the invention is to provide a semiconductor integrated circuit technique capable of improving the yield by efficiently repairing a defective bit in a memory circuit in a semiconductor integrated circuit having therein a plurality of memory circuits such as RAMs.
Another object of the invention is to provide a semiconductor integrated circuit having therein a plurality of memory circuits, with an increased operation margin by adjusting a timing of accessing a memory circuit, capable of accessing a memory circuit at higher speed.
Further another object of the invention is to provide a semiconductor integrated circuit having a general bus method commonly used for diagnosing memories and setting memory characteristics.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the appended drawings.
The outline of representative ones of inventions disclosed in the application will be described as follows.
A semiconductor integrated circuit according to the invention comprises: a plurality of circuit blocks each having an identification code coincidence detecting circuit for determining whether an input identification code matches with a self identification code or not and a reception data latch or holding circuit and performing an operation according to data latched; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the setting information from the setting circuit, converting the read setting information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the transferred setting information by the corresponding reception data latch when the identification code coincidence detecting circuit determines that the input identification code and the self identification code match with each other.
According to the means, the setting of repair address information, timing information, or the like can be changed in each of the circuit blocks in the semiconductor integrated circuit after the manufacture of the semiconductor integrated circuit, thereby enabling the performance of each circuit block to be maximally drawn out. Further, the setting circuit for setting information to be held by the plurality of circuit blocks can be shared by the plurality of circuit blocks, so that the scale of the setting circuit can be largely reduced. Since the setting information of the setting circuit is read as serial data by using the serial bus, an information amount which can be set in the setting circuit can be increased without changing the control circuit. Further, it is sufficient to transfer the setting information of the setting circuit to each of the circuit blocks once at the time of, for example, start-up of the system. Consequently, the throughput does not deteriorate due to the serial transfer method.
Desirably, the setting information is transferred from the control circuit to the plurality of circuit blocks via a parallel bus. With the configuration, a plurality of signal lines in the parallel bus for transferring the setting information from the setting circuit to the plurality of circuit blocks can be commonly used. As compared with the case where a signal line dedicated to transfer the setting information to each of the circuit blocks is provided, the number of signal lines can be largely reduced.
The setting circuit has a plurality of program elements or program devices which can be programmed from the outside and a shift register for reading states of the program devices in parallel and serially transferring the read states. With the configuration, arbitrary information can be set after manufacture of the semiconductor integrated circuit, and information set in the setting circuit can be efficiently read.
Further, the shift register performs a shifting operation in accordance with a clock signal for shifting supplied from the control circuit. Consequently, the setting information can be automatically transferred without externally generating a clock signal for shifting and supplying the signal.
Preferably, a plurality of terminals to which information can be input from the outside of the semiconductor integrated circuit are provided, and the control circuit can transfer either information input from the plurality of terminals or information set in the setting circuit to the plurality of circuit blocks by using the parallel bus. With the configuration, before information is set in the setting information, the setting information is held by each of the circuit blocks and a test operation is performed to preliminarily check whether the setting information is appropriate or not. Thus, erroneous setting can be avoided. Since the parallel bus is commonly used, the circuit scale can be prevented from being enlarged.
When each of the plurality of circuit blocks is a memory circuit having a redundancy circuit for replacing a memory cell having a defect with a spare memory cell, the reception data latch captures and holds a repair address which makes the redundancy circuit valid. When a single semiconductor integrated circuit has therein a plurality of memory circuits and each memory circuit has a redundancy circuit, if a repair address setting circuit including program elements
Hayashi Hideki
Higeta Keiichi
Nakahara Shigeru
Suzuki Takeshi
Hitachi , Ltd.
Hoang Huan
Miles & Stockbridge P.C.
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