Semiconductor integrated circuit

Electronic digital logic circuitry – Tri-state – With field-effect transistor

Reexamination Certificate

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Details

C326S030000, C326S086000, C326S087000, C327S109000, C327S112000, C327S551000, C365S193000

Reexamination Certificate

active

07999572

ABSTRACT:
Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

REFERENCES:
patent: 5467455 (1995-11-01), Gay et al.
patent: 6380758 (2002-04-01), Hsu et al.
patent: 7808269 (2010-10-01), Matsudera
patent: 2003/0039151 (2003-02-01), Matsui
patent: 2003/0080774 (2003-05-01), Funaba
U.S. Appl. No. 12/876,747, filed Sep. 7, 2010, Komyo et al.
U.S. Appl. No. 12/876,760, filed Sep. 7, 2010, Komyo et al.
JEDEC STANDARD, DDR2 SDRAM Specification, JESD79-2E (Revision of JESD79-2D), JEDEC Solid State Technology Association, Apr. 2008, 125 pages.
Masayasu Komyo et al., USPTO Office Action, U.S. Appl. No. 12/876,747, Feb. 2, 2011, 10 pages.

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