Semiconductor integrated circuit

Electronic digital logic circuitry – Reliability – Redundant

Reexamination Certificate

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Details

C326S016000, C326S096000, C714S724000, C714S726000, C714S734000

Reexamination Certificate

active

07902856

ABSTRACT:
An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target.

REFERENCES:
patent: 4975640 (1990-12-01), Lipp
patent: 5281864 (1994-01-01), Hahn et al.
patent: 5504756 (1996-04-01), Kim et al.
patent: 6691268 (2004-02-01), Chin
patent: 56-168268 (1981-12-01), None

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