Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2011-03-15

2011-03-15

Phung, Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Amorphous

C365S207000

Reexamination Certificate

active

07907442

ABSTRACT:
In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively. Therefore, when the first and second signal lines are varied and the separated state is released upon a read operation, the first MOS transistors start to operate in a saturated region, thereby realizing a high-speed read operation.

REFERENCES:
patent: 7280391 (2007-10-01), Kang et al.
patent: 7397695 (2008-07-01), Nakai et al.
patent: 7453715 (2008-11-01), Parkinson
patent: 10-050072 (1998-02-01), None
patent: 2001-216794 (2001-08-01), None
patent: 2003-173686 (2003-06-01), None

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