Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-06-23

2001-10-30

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S058000, C326S068000, C327S333000

Reexamination Certificate

active

06310493

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having input-output circuit having complementary metal oxide semiconductor (CMOS) structure. More particularly, this invention relates to a semiconductor integrated circuit capable of exchanging signals easily between circuits with other semiconductor integrated circuits driven by mutually different supply voltages.
BACKGROUND OF THE INVENTION
FIG. 14
is a circuit diagram of an input-output circuit in a conventional semiconductor integrated circuit with a signal level converting function. The signal level converting function in such a semiconductor integrated circuit means the following two functions.
(1) Converting the level of signal voltage issued from an internal circuit operated at a supply voltage of the semiconductor integrated circuit, and supplying the newly obtained voltage to an external circuit operated at a supply voltage different from this supply voltage (that is, an internal circuit of other semiconductor integrated circuit); and
(2) Converting the level of signal voltage received from an external circuit operated at a supply voltage different from the supply voltage of the semiconductor integrated circuit, and supplying the newly obtained voltage to an internal circuit.
The input-output circuit shown in
FIG. 14
includes an output buffer circuit
12
h
, an electrostatic protective circuit
8
, and an input buffer circuit
9
. As shown in
FIG. 14
, theoutput buffer circuit
12
h
is composed of an input circuit unit
10
h
and an output circuit unit
11
h
. The input circuit unit
10
h
is classified into a circuit unit operated at a first supply potential VDD
1
and a circuit unit operated at a second supply potential VDD
2
.
As shown in
FIG. 14
, the input circuit unit
10
h
is divided into two sections of a first signal processing unit and a second signal processing unit. The first signal processing unit receives a data input signal IN
1
issued from the internal circuit into an input terminal
1
and processes this data input signal IN
1
. The second signal processing unit receives an output control signal IN
2
issued from the internal circuit into a control terminal
2
and processes this output control signal IN
2
.
The first signal processing unit is composed of a PMOS transistor MP
111
, an NMOS transistor MN
111
, a PMOS transistor MP
112
, an NMOS transistor MN
112
, and an inverter G
111
. The PMOS transistor MP
111
has its source connected to the second supply potential VDD
2
. The NMOS transistor MN
111
has its source connected to the grounding potential GND, drain connected to the drain of the PMOS transistor MP
111
and gate connected to the input terminal
1
. The PMOS transistor MP
112
has its source connected to the second supply potential VDD
2
, and gate connected to the drain of the NMOS transistor MN
111
. The NMOS transistor MN
112
has its drain connected to the gate of the PMOS transistor MP
111
and the drain of the PMOS transistor MP
112
. The input terminal of the inverter G
111
is connected to the input terminal
1
and the output terminal is connected to the gate of the NMOS transistor MN
112
. The point where the gate of the PMOS transistor MP
111
, the drain of the PMOS transistor MP
112
, and the drain of the NMOS transistor MN
112
are connected to each other will be referred to as node N
111
.
Thus, the first signal processing unit is a circuit which converts the level of the data input signal IN
1
received from the internal circuit and supplies the newly obtained signal to the node N
111
.
On the other hand, the second signal processing unit is composed of a PMOS transistor MP
113
, an NMOS transistor MN
113
, a PMOS transistor MP
114
, an NMOS transistor MN
114
, and an inverter G
112
. The PMOS transistor MP
113
has its source connected to the second supply potential VDD
2
. The NMOS transistor MN
113
has its source connected to the grounding potential GND, drain connected to the drain of the PMOS transistor MP
113
and gate connected to the control terminal
2
. The PMOS transistor MP
114
has its source connected to the second supply potential VDD
2
, and gate connected to the drain of the NMOS transistor MN
113
. The NMOS transistor MN
114
has its drain connected to the gate of the PMOS transistor MP
113
and the drain of the PMOS transistor MP
114
. The input terminal of the inverter G
112
is connected to the control terminal
2
and the output terminal is connected to the gate of the NMOS transistor MN
114
. The point where the gate of the PMOS transistor MP
113
, the drain of the PMOS transistor MP
114
, and the drain of the NMOS transistor MN
114
are connected to each other will be referred to as node N
112
.
Thus, the second signal processing unit is a circuit which converts the level of the output control signal IN
2
received from the internal circuit and supplies the newly obtained signal to node N
112
.
In particular, the first and second signal processing units operate, supposing the operating voltage of the internal circuit to be first supply potential VDD
1
, as a latch signal level converting circuit which converts the level of the signal of the first supply potential VDD
1
level into a signal of the second supply potential VDD
2
level.
As mentioned above, the input circuit unit
10
h
is divided into a circuit which operates at the first supply potential VDD
1
and a circuit which operates at the second supply potential VDD
2
. The former circuit comprises the inverters G
111
and G
112
. The latter circuit comprises the PMOS transistors MP
111
and MP
112
, NMOS transistors MN
111
and MN
112
, PMOS transistors MP
113
and MP
114
, and NMOS transistors MN
113
and MN
114
.
In
FIG. 14
, the symbol “VDD
1
←” indicates the circuit that operates at the first supply potential VDD
1
which is the supply voltage of the internal circuit. On the other hand, and the symbol “→VDD
2
” indicates the circuit that operates at the second supply potential VDD
2
. Although the internal circuit is not shown in this diagram, this internal circuit operates at the first supply potential VDD
1
. Further, an output circuit unit
11
h
, which will be explained below, operates at the second supply potential VDD
2
. It is assumed here that a relation of VDD
2
>VDD
1
>GND holds.
The output circuit unit
11
h
is composed of an inverter G
113
, a two-input NAND gate G
114
, a two-input NOR gate G
115
, a PMOS transistor MP
115
, and an NMOS transistor MN
115
. The inverter G
113
has its input terminal connected to the node N
112
. The two-input NAND gate G
114
has one of its input terminals connected to the node N
111
and the other input terminal connected to the output terminal of the inverter G
113
. The two-input NOR gate G
115
has one of its input terminals connected to the node N
111
and the other input terminal connected to the node N
112
. The PMOS transistor MP
115
has its source connected to the second supply potential VDD
2
and gate connected to the output terminal (node N
114
) of the NAND gate G
114
. The NMOS transistor MN
115
has its drain connected to the drain of the PMOS transistor MP
115
, its source connected to the grounding potential GND, and its gate connected to the output terminal (node N
115
) of the NOR gate G
115
. This output circuit unit
11
h
operates on the second supply potential VDD
2
.
The gate insulating film of the MOS transistors which compose the PMOS transistors MP
111
to MP
115
, NMOS transistors MN
111
to MN
115
, inverter G
113
, NAND gate G
114
, and NOR gate G
115
is thicker than the gate insulating film of the MOS transistors which compose the inverters G
111
and G
112
. Such an arrangement is provided in order to prevent damage of the gate insulating films of these MOS transistors.
The electrostatic protective circuit
8
is connected to the input-output terminal
3
(PAD terminal). This electrostatic protective circuit
8
functions to protect the output buffer circuit
12
h
from electrostatic breakdown in the following manner. That is, when an input

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