Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-01-09
2001-12-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S086000, C326S113000
Reexamination Certificate
active
06329844
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit which is used for general purpose or special purpose. More to particularly, this invention relates to a semiconductor integrated circuit which is appropriately used as a drive circuit for driving long wiring in high speed or a reception circuit for receiving signal through the long wiring.
Description of the Prior Art
Formerly, in the semiconductor integrated circuit using CMOS (Complementary Metal Oxide Semiconductor) and so forth, CMOS domino logic reported in pp. 143 of “Principles of CMOS VLSI Design” published by Maruzen Co., Ltd., (Author: Neil H. E. Weste & Kamran Eshraghian) is well known as a method for achieving realization of high speed operation and a method for achieving realization of reduced area.
FIG. 1
is a circuit diagram showing a constitution of a drive circuit consisting of such kind of conventional semiconductor integrated circuit.
In
FIG. 1
, a reference numeral
10
shows a logic circuit. The logic circuit consists of n-type (n-channel) MOS transistors. The logic circuit consists of p-type (p-channel) MOS transistors. The logic circuit consists of both of n-type MOS transistor and p-type MOS transistor. Reference numerals
11
, and
17
show n-type (n-channel) MOS transistors. Reference numerals
14
,
15
, and
18
show p-type (p-channel) MOS transistors. A reference character ‘S’ shows source. A reference character ‘D’ shows drain. A reference character ‘G’ shows gate. A reference numeral
20
shows an input terminal to which clock and so forth are inputted. Reference numerals
21
, and
22
show data input terminals to which data and so forth are inputted. A reference numeral
24
shows an output terminal. Reference numerals
40
,
41
show ground (earth). Reference numerals
42
,
43
, and
44
show electric power-supply Vdd.
In a circuit connection constitution as shown in
FIG. 1
, an inverter
19
is constituted by an n-type MOS transistor
17
and a P-type MOS transistor
18
. A p-type MOS transistor
15
has feeble drive power. The p-type MOS transistor
15
always maintains ON-state. However, the p-type MOS transistor
15
does not influence operation of the semiconductor integrated circuit.
Here, a signal is supplied Lo the input terminal
20
. When level of signal is Low-level, the n-type MOS transistor
11
becomes OFF-state. Simultaneously, the p-type MOS transistor
14
becomes ON-state. Consequently, level of an input of the inverter
19
becomes H-level. As a result, level of a signal which is outputted from the output terminal
24
becomes L-level.
Next, level of the signal supplied to the input terminal
20
becomes H-level. The logic circuit
10
becomes ON-state according to combination between the data input terminals
21
, and
22
. On the occasion of this condition, level of the logic circuit and level of an input node of the inverter
19
through the n-type MOS transistor
11
become L-level, thus level of the output becomes H-level.
Now, in the above-described conventional drive circuit, a transistor causes level of the output terminal
24
to be driven to H-level. The above-described transistor is the p-type MOS transistor
18
. The drive power of the p-type MOS transistor
18
is smaller than that of the n-type MOS transistor. A p-type MOS transistor
18
with large drive power is required for the case where long wiring is driven. As a result, if the p-type MOS transistor with large power is used, occupied area of the p-type MOS transistor becomes large. So there occurs the problem that response speed lowers. This problem becomes a main cause that blocks realization of high speed operation and realization of reduced area of the whole semiconductor integrated circuit.
On the other hand, there is a reception circuit. The reception circuit receives signal through the long wiring from the conventional drive circuit described-above. When such the reception circuit is constituted, a regular inverter is used. However, when wave-form change of input is gentle, through-current flows in the inverter. Thus there is the problem that delay time becomes large.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention, in order to overcome the above-mentioned problem, to provide a semiconductor integrated circuit which is capable of constituting both of a drive circuit that enables long wiring to be driven in high speed while achieving reduced area and a reception circuit for receiving signal thereof in high speed.
According to a first aspect of the present invention, in order to achieve the above mentioned object, there is provided a semiconductor integrated circuit which comprises a first p-type MOS transistor whose source is connected to an electric power-supply, whose gate is connected to a first input terminal, and whose drain is connected to a first node respectively, a second p-type MOS transistor whose source is connected to the electric power-supply, whose gate is connected to a second node, and whose drain is connected to the first node respectively, a logic circuit consisting of plural n-type MOS transistors to which a second input terminal, ground, and the first node are connected respectively, a first inverter in which the first node is taken to be an input, and the second node is taken to be an output, a first n-type MOS transistor whose drain is connected to the electric power-supply, whose gate is connected to the second node, and whose source is connected to a first output terminal respectively, and a second n-type MOS transistor whose source is connected to the ground, whose gate is connected to the first node, and whose drain is connected to the first output terminal respectively.
According to a second aspect of the present invention, in the first aspect, there is provided a semiconductor integrated circuit, wherein the logic circuit is connected to a third node, and to the ground through a third n-type MOS transistor; and source of the third n-type MOS transistor is connected to ground, gate of the third n-type MOS transistor is connected to the first input terminal, and drain of the third n-type MOS transistor is connected to the third node respectively.
According to a third aspect of the present invention, in the first or the second aspects, there is provided a semiconductor integrated circuit, wherein the semiconductor integrated circuit is constituted as a drive circuit for driving an external circuit.
According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit which comprises a first p-type MOS transistor whose source is connected to an electric power-supply, whose gate is connected to a first node, and whose drain is connected to a second node respectively, a second p-type MOS transistor whose source is connected to the second node, whose gate is connected to a first input terminal, and whose drain is connected to a first output terminal respectively, a first n-type MOS transistor whose source is connected to ground, whose gate is connected to a fifth node, and whose drain is connected to a third node respectively, a second n-type MOS transistor whose source is connected to the third node, whose gate is connected to the first input terminal, and whose drain is connected to the first output terminal respectively, and a logic circuit in which the first output terminal and the second input terminal are taken to be an input, and the first node and the fifth node are taken to be an output.
According to a fifth aspect of the present invention, in the fourth aspect, there is provided a semiconductor integrated circuit, which further comprises a first inverter in which the first output terminal is taken as an input, and a fourth node is taken as an output, and a second inverter in which the fourth node is taken to be an input, and a first output terminal is taken to be an output.
According to a sixth aspect of the present invention, in the fourth or the fifth aspect, there is provided a semiconductor integrated circuit, wherein the semiconductor
NEC Corporatation
Paik Steven S.
Tokar Michael
Young & Thompson
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