Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1998-11-18

2001-08-07

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S088000, C326S017000

Reexamination Certificate

active

06271685

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor IC (Integrated Circuit) having a pass transistor logic circuit. More particularly, the present invention relates to a semiconductor IC with an improved production yield and a reduced cost.
2. Description of the Related Art
In recent years, there have been growing demands for reducing power consumption, increasing an operating speed and reducing a chip area of a semiconductor IC. In order to meet such demands, “White paper on low power consumption LSIs”, pp.98-104, Nikkei Business Publications Inc., for example, has proposed a circuit configuration using a pass transistor logic.
In the pass transistor logic circuit proposed in this publication, a logic circuit is formed by NMOS transistors, whereby transmission of a low level signal is desirable. However, a voltage level of a high level signal being output is reduced by a threshold value of the NMOS transistor due to a substrate effect.
In view of this, other conventional pass transistor logic circuits have been proposed, as will be described below, which employ various measures to pull up the reduced high level signal (which has been reduced by the threshold value of the NMOS transistor) to the desired high level. This is done to obtain a sufficient driving capacity for a subsequent-stage circuit.
A CPL (Complementary Pass-Transistor Logic) proposed by Hitachi Ltd. has been proposed with a CMOS inverter at an output section for restoring a blunted high logic level to its original level, and a PMOS cross-coupled latch for suppressing a static current of the CMOS inverter, thereby augmenting the driving force for a subsequent-stage load. For more details, see “K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, “A 3.8 ns CMOS 16×16-b Multiplier Using Complementary Pass-Transistor Logic”, IEEE J. Solid-State Circuits., Vol. 25, No. 2, pp. 388-395 (1990)”.
Another conventional example is an SRPL (Swing Restored Pass-Transistor Logic) proposed by Toshiba Corporation, which uses a CMOS latch for ensuring that the output reaches the desired level. For more details, see “A. Parameswar, H. Hara and T. Sakurai, “A high Speed, Low Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications”, Proc. IEEE 1994 CICC, pp. 278-281, May 1994.
In these conventional pass transistor logic circuits, a CMOS buffer is provided for every predetermined number of serially-connected transistors for restoring a signal level.
Thus, conventionally, in order to reduce power consumption, increase an operating speed and reduce a chip area of an LSI using a pass transistor logic circuit in place of a CMOS logic circuit, a PMOS transistor is necessary for driving a high level signal.
However, a PMOS transistor has an operating speed which is about {fraction (1/3+L )} of that of an NMOS transistor due to the carrier mobility difference therebetween. This spoils the characteristic of a pass transistor logic circuit being faster than a CMOS logic circuit.
Conventionally, in order to increase the operating speed of the PMOS transistor to a level comparable to that of an NMOS transistor, it is necessary to provide a PMOS transistor which is larger than an NMOS transistor. However, this makes it difficult to reduce the chip area.
In addition, since a logic circuit in the pass transistor logic circuit is formed by NMOS transistors, the relative size of the NMOS transistor region with respect to the PMOS transistor region is often larger as compared with that of a CMOS logic circuit. Therefore, with a layout method conventionally used in a CMOS process, some area is likely to be wasted in a P well. As a result, the chip area for a certain number of transistors is likely to be larger than that in the conventional CMOS logic circuit.
For the two reasons set forth above, it has been difficult to reduce the chip area in a semiconductor IC using the conventional pass transistor logic circuit.
SUMMARY OF THE INVENTION
According to one aspect of this invention, a semiconductor integrated circuit includes: a pass transistor logic circuit; and an output buffer for compensating for an output level of the pass transistor logic circuit, wherein the output buffer comprises a bootstrap circuit.
In one embodiment of the invention, the bootstrap circuit is additionally provided with a driving force complementary transistor.
In one embodiment of the invention, the pass transistor logic circuit consists of NMOS transistors.
Features of the present invention will now be described.
The present invention employs a bootstrap circuit for restoring a blunted high level output of a pass transistor logic circuit so as to obtain a sufficient drive capacity of the high level signal for a subsequent-stage circuit.
By using the bootstrap circuit, it is possible to increase a high level output which has been blunted through an NMOS transistor to a power supply voltage (V
DD
) without using a PMOS transistor, as illustrated in
FIGS. 1 and 2
.
As a result, according to the present invention, a pass transistor logic circuit can be formed only with NMOS transistors, whereby it is possible to reduce the chip area as compared with the conventional pass transistor logic circuit which uses a PMOS transistor as necessary. Thus, it is possible to reduce the chip area of the pass transistor logic circuit while reducing the power consumption and increasing the operating speed.
In addition, according to the present invention, it is possible to produce a semiconductor IC with a conventional NMOS process, which is simpler than the CMOS process, thereby considerably reducing the turn around time.
Moreover, a PMOS region is not necessary, which also facilitates the reduction of the chip area.
Furthermore, when a driving force complementary transistor is additionally provided, the power consumption of the semiconductor IC can be further reduced for reasons set forth in the following description of the preferred embodiments.
Thus, the invention described herein makes possible the advantage of providing a semiconductor IC in which a chip area can be reduced while reducing the power consumption and increasing the operating speed, thereby improving the production yield thereof and reducing the cost therefor.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.


REFERENCES:
patent: 3774055 (1973-11-01), Bapat
patent: 3845324 (1974-10-01), Feucht
patent: 3898479 (1975-08-01), Proebsting
patent: 4316106 (1982-02-01), Young et al.
patent: 4408136 (1983-10-01), Kirsh
patent: 4443720 (1984-04-01), Takemae
patent: 4446567 (1984-05-01), Iida et al.
patent: 4500799 (1985-02-01), Sud et al.
patent: 4570085 (1986-02-01), Redfield
patent: 4622479 (1986-11-01), Taylor
patent: 5184035 (1993-02-01), Sugibayashi
patent: 5327026 (1994-07-01), Hardee et al.
patent: 5654660 (1997-08-01), Orgill et al.
patent: 5694061 (1997-12-01), Morosawa et al.
patent: 5917348 (1999-06-01), Chow
patent: 58-162126 (1983-09-01), None
“XP002097267 Enhancement/Depletion Decoder Circuit,” Dockerty et al., IBM Technical Disclosure Bulletin, vol. 19, No. 5, Oct. 1976, pp. 1681-1682.
“XP002097268 Dynamic depletion circuits upgrade MOS performance,” Clay Cranford, Electronics, vol. 54, No. 13, Jun. 1981, pp. 128-129.
“XP-002097269 Pass Transistor Realization of a General Boolean Function,” M. Y. Tsai, IBM Technical Disclosure Bulletin, vol. 26, No. 1, Jun. 1983, pp. 35-39.
Nikkei Business Publication “White paper on low power consumption LSIs”; pp. 98-106; 1994.
Akilesh Parameswar et al. “A High Speed, Low Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit For Multimedia Applications”, PROC. IEEE 1994 CICC, pp. 278-281, May 1994.
K. Yano et al. “A 3.8-ns CMOS 16×16-b Multiplier Using Complementary Pass-Transistor Logic”, IEEE J. Solid-State Circuits., vol. 25, No. 2, pp. 388-395, Apr. 1990.

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