Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1999-10-14

2001-03-06

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S201000, C365S233100

Reexamination Certificate

active

06198669

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit incorporating a large-capacity memory and, more particularly, to a semiconductor integrated circuit capable of realizing downsizing of a package and reduction in number of inspection patterns.
2. Description of the Prior Art
Semiconductor integrated circuits incorporating memories have conventionally been provided. When the incorporated memory of such a semiconductor integrated circuit is to be tested, to supply an address signal indicating the address in the memory or a data signal as data to be written at this address of the memory, these signals must be supplied from the outside by an LSI tester or the like.
For this reason, a conventional semiconductor integrated circuit needs externally connectable pins in a number proportional to the memory capacity, and the number of pins increases in accordance with an increase in memory capacity. When the number of pins increases in this manner, downsizing of the package is interfered with. When the number of pins of the semiconductor integrated circuit increases, the number of probes of the LSI tester also increases, leading to an increase in cost of the test process.
In order to cope with these problems, for example, an integrated circuit disclosed in Japanese Unexamined Patent Publication No. 5-289953 has, regarding an address signal, a counting means and a decoding means. The counting means counts continuously input clock signals. The decoding means decodes a count output from the counting means to generate a select signal that specifies one memory among a plurality of memories, and to generate the address of the specified memory. The package of the integrated circuit accordingly requires neither a test address input pin nor a memory select pin.
FIG. 1
is a block diagram of the integrated circuit disclosed in this Japanese Unexamined Patent Publication No. 5-289953.
This integrated circuit has, as pins to be connected to the outside, a data input pin
1
, clock (CLK) pin
2
, test reset pin
3
, test mode pin
4
, and data output pin
5
. Each of memories
6
,
7
,
8
, and
9
is a RAM or ROM. Data from the memory
6
,
7
,
8
, or
9
is selected by an output selector
13
that has received an output select signal S
1
from a control circuit
10
, and is output from the data output pin
5
.
The control circuit
10
has a memory address generating counter
11
and memory selector
12
. The memory address generating counter
11
counts clock pulses input from the clock pin
2
. The count of the memory address generating counter
11
forms an address signal S
2
indicating the memory address of either one of the memories
6
,
7
,
8
, and
9
. The memory selector
12
outputs an output select signal that selects either one of the memories
6
,
7
,
8
, and
9
upon reception of a predetermined bit of the count of the memory address generating counter
11
.
Referring to
FIG. 1
, in this conventional integrated circuit, as data to be written in the memory
6
,
7
,
8
, or
9
, test data is supplied from the data input pin
1
. In order to inspect whether the data written in the memory
6
,
7
,
8
, or
9
is correct, the written data is read out from the memory
6
,
7
,
8
, or
9
to output data, and the output data is compared with the input data.
For this reason, in this conventional integrated circuit, a data input pin equivalent to the bit width of the incorporated memory is required. As the bit width of the memory increases, the number of pins increases to accordingly interfere with downsizing of the package.
Furthermore, in order to input/output the test data, the number of inspection patterns increases in proportion to the memory capacity. Accordingly, the test time required for inspection prolongs to increase the cost of inspection.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation in the prior art, and has as its object to provide a semiconductor integrated circuit in which the package can be further downsized and the number of inspection patterns can be reduced.
In order to achieve the above object, according to the main aspect of the present invention, there is provided a semiconductor integrated circuit comprising: an incorporated memory unit; a first register unit for storing data to be written in the memory unit as a test circuit for the memory unit; a second register unit for storing a value read out from the memory unit; a comparator unit for comparing values of the first and second register units with each other; and address generator for generating an address signal of the memory unit on the basis of an external input clock pulse.
According to the arrangement of the main aspect described above, since a memory address signal and a data signal need not be input from or output to the outside for performing the memory test, a memory data line and a memory address line need not be connected to the terminals of the LSI. Therefore, the number of pins can be reduced, realizing downsizing of the package.
The data signal and memory address signal for the memory test are generated in the semiconductor integrated circuit. Whether the memory unit operates correctly can be checked by referring to only the result of the comparator unit, and only a clock need be supplied from the outside. The number of patterns for inspection by the LSI tester can accordingly be reduced. As a result, the test time can be decreased to reduce the cost.
According to the arrangement of the main aspect described above, even when the capacity of the incorporated memory increases and a plurality of memories are provided, the number of pins connected to the outside does not increase, contributing to downsizing of the package. Also, the cost in the test process can be reduced.
In addition to the main aspect described above, the present invention also has the following auxiliary aspects.
According to the first auxiliary aspect, there is provided a semiconductor integrated circuit wherein the memory unit according to the above main aspect comprises a plurality of memories, and the address generator includes a memory selector for selecting, among the memories, a specific one on the basis of a clock pulse.
According to the second auxiliary aspect, there is provided a semiconductor integrated circuit comprising a write control unit for writing data stored in the first register unit, at an address corresponding to an address signal generated by the address generator according to the main aspect described above.
According to the third auxiliary aspect, there is provided a semiconductor integrated circuit comprising a read control unit for storing data read out from an address corresponding to an address signal generated by the address generator according to the main aspect described above, in the second register unit.
According to the fourth auxiliary aspect, there is provided a semiconductor integrated circuit wherein the write control unit according to the second auxiliary aspect described above writes the data stored in the first register unit, in the plurality of memories simultaneously.
According to the fifth auxiliary aspect, there is provided a semiconductor integrated circuit wherein the address generator according to the main aspect described above has a counter for counting the number of clock pulses, and part or all of a count of the counter forms an address signal.
According to the sixth auxiliary aspect, there is provided a semiconductor integrated circuit wherein each of the first and second register units according to the main aspect described above comprises a plurality of registers.
According to the seventh auxiliary aspect, there is provided a semiconductor integrated circuit wherein a decoder is provided between the address generator and the memory unit so that all of the memories can be selected in a data write in the plurality of memories according to the first auxiliary aspect described above, and a memory can be selected from the plurality of memories in a data r

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