Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-10-28
2001-03-27
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C257S202000
Reexamination Certificate
active
06208165
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit laid out in accordance with a standard cell system.
2. Description of Related Art
Recently, when a semiconductor integrated circuit is designed, a so called standard cell system is used as a layout method. In brief, a number of standard cells having various logic functions are previously prepared, and the standard cells are located in accordance with a designed logic circuit, so that a standard cell array is formed. Furthermore, a plurality of standard cell arrays thus formed are located, and then, interconnections for ordinary signals supplied to the standard cell arrays and/or transferred between the standard cell arrays, and interconnections for clock signals supplied to the logic circuits, are laid out.
Now, a method for designing a semiconductor integrated circuit in accordance with a conventional standard cell system will be described with reference to FIG.
5
.
As shown in
FIG. 5
, a plurality of standard cell arrays
9
,
10
and
11
are located in accordance with a designed logic circuit. Each of the standard cell arrays
9
,
10
and
11
has terminals for a clock signal provided on one side thereof and terminals for an ordinary signal provided on a side thereof opposite to the first mentioned side. For example, the standard cell array
9
includes terminals T
1
for a clock signal and terminals T
4
for an ordinary signal.
In addition, a clock signal interconnection
12
to be connected to the terminals on the respective side of these standard cell arrays, and an ordinary signal interconnection
13
for transferring the ordinary signals between the standard cell arrays, are located, and connected to necessary terminals provided on the sides of the standard cell arrays.
Now, this will be explained in detail with reference to FIG.
6
.
FIG. 6
is a diagrammatic plan view of one standard cell
14
included in the standard cell array
9
, and connected to the clock signal interconnection
12
and the ordinary signal interconnection
13
. The content of the standard cell is various and different from one standard cell to another. The shown example is a standard cell including two transistors receiving a clock signal and an ordinary signal.
As shown in
FIG. 6
, the clock signal interconnection
12
is connected to the standard cell
14
at the terminal T
1
positioned at an upper side of the standard cell in the drawing. On the other hand, the ordinary signal interconnection
13
is connected to the standard cell
14
at the terminal T
4
positioned at a lower side of the standard cell in the drawing.
Since there is possibility that each of the clock signal interconnection
12
and the ordinary signal interconnection
13
exists on both opposite sides of the standard cell array, the standard cell has the clock signal terminal T
1
and an ordinary signal terminal T
2
provided on the upper side of the standard cell and a clock signal terminal T
3
and the ordinary signal terminal T
4
provided on the lower side of the standard cell. However, all of the terminals T1 to T4 were never used without exception. For example, in the example shown in
FIG. 6
, the terminals T
2
and T
3
are not used.
However, when the standard cell as shown in
FIG. 6
is used, the following problem has been encountered.
Namely, in the standard cell, a clock is supplied from the clock signal terminal T
1
through an internal interconnection
15
a
to an internal element, for example, a transistor. In this case, the terminal T
3
is not used. The clock signal is supplied from the internal interconnection
15
a
through contacts to an interconnection of another level. However, an interconnection portion
15
b
between a contact C
1
and the terminal T
3
is of no use at all.
This useless interconnection
15
b
exists in each of the standard cells. The useless interconnection becomes a considerable amount for each of the standard cell arrays. This means that the clock signal interconnection
12
meaninglessly includes an excessive parasitic capacitance. Therefore, if the conventional standard cells are used, unnecessary parasitic capacitance is generated, with the result that a speeding-up of a circuit operation is obstructed, and a clock skew occurs.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit which has overcome the above mentioned problem of the prior art.
Another object of the present invention is to provide a semiconductor integrated circuit including standard cells capable of minimizing the parasitic capacitance accompanying the interconnection, so that a high speed operation can be obtained.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor integrated circuit including a plurality of standard cells which are arranged in an array direction to constitute a logic circuit and which are supplied with a clock signal, each of the standard cells having a first side and a second side opposite to each other and extending in the array direction, each of the standard cells having on only the first side a clock signal terminal for receiving the clock signal, each of the standard cells having no internal interconnection which is used to supply the clock signal within the standard cell and which reaches the second side of the standard cell.
In one embodiment, the first side of each of the standard cells includes a first ordinary signal terminal for receiving and/or sending an ordinary signal, in addition to the clock signal terminal for receiving the clock signal, and the second side of each of the standard cell includes a second ordinary signal terminal for receiving and/or sending an ordinary signal.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit including a plurality of standard cells which are arranged in an array direction to constitute a logic circuit and which are supplied with a clock signal, each of the standard cells having a first side and a second side opposite to each other and extending in the array direction, each of the standard cells having on only the first side a clock signal terminal for receiving the clock signal, the second side of each of the standard cells having no terminal for receiving the clock signal.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit including a plurality of standard cells which are arranged in an array direction to constitute a logic circuit and which are supplied with a clock signal, each of the standard cells having a first side and a second side opposite to each other and extending in the array direction, each of the standard cells having on only the first side a clock signal terminal connected to a clock signal interconnection for receiving the clock signal, each of the standard cells having no internal interconnection extending between the second side and a contact which connects an internal interconnection connected to the clock signal terminal and for supplying the clock signal within the standard cell, an interconnection of another level.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.
REFERENCES:
patent: 4701778 (1987-10-01), Aneha et al.
patent: 5045725 (1991-09-01), Sasaki et al.
patent: 5237184 (1993-08-01), Yonemaru et al.
patent: 5468977 (1995-11-01), Machida
patent: 5532501 (1996-07-01), Nakemura
patent: 03-69163 (1991-03-01), None
patent: 09-191052 (1997-07-01), None
patent: 10-107236 (1998-04-01), None
Cho James H.
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Tokar Michael
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