Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1997-05-27

2001-04-24

Santamauro, Jon (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

C326S124000

Reexamination Certificate

active

06222391

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor and, more particularly, to an ECL (Emitter Coupled Logic) integrated circuit.
Semiconductor integrated circuits using bipolar transistors for transmitting logic signals are generally classified into TTL circuits, ECL circuits, and others. In TTL circuits, high potential levels range from 2.4 V to 2.5 V, low potential levels range from 0 V to 0.4 V. In ECL circuits, potential levels are −0.7 V to −1.9 V, and amplitudes are around 1 V, which are largely different from those of TTL circuits and require different usages.
FIG. 4
is a circuit diagram of a conventional differential ECL circuit, and
FIG. 5
is an explanatory diagram schematically showing potentials at internal nodes in the differential ECL circuit of
FIG. 4
when the base-emitter voltage V
BE
of npn bipolar transistors is 0.9 V and the reference potential GND is 0 V.
Construction of the differential ECL circuit is explained below.
Resistors R
1
, R
2
are supplied at their first ends with the reference potential GND, which is typically the ground potential. Connected to the other ends of the resistors R
1
and R
2
are collectors of npn bipolar transistors Q
1
and Q
2
. Introduced to bases of these two npn bipolar transistors Q
1
, Q
2
are input signals IN and /IN (/ denotes inverted signal) of potential levels between −0.9 V and −1.7 V. Commonly connected emitters of the npn bipolar transistors Q
1
, Q
2
are connected to one end of a resistor R
3
, and the power source potential V
EE
is applied to the other end of the resistor R
3
. These elements form a current switch S
1
, and output from the current switch S
1
is used as input to an emitter follower. That is, bases of npn bipolar transistors Q
3
, Q
4
whose collectors are supplied with the reference potential GND are connected to the connection node of a resistor R
1
and the collector of the npn bipolar transistor Q
1
and the connection node of a resistor R
2
and the collector of the npn bipolar transistor Q
2
. Emitters of the npn bipolar transistors Q
3
, Q
4
are connected to given ends of resistors R
4
, R
5
whose other ends are supplied with the power source potential V
EE
. Output signals OUT and /OUT of the differential ECL circuit are taken out from connection nodes of the npn bipolar transistors Q
3
, Q
4
and given ends of resistors R
4
, R
5
. The resistors R
1
and R
2
have the same resistance value R.
In the conventional differential ECL circuit, input signals IN and /IN of potential levels from −0.9 V to −1.7 V are introduced to the current switch S
1
. Among two npn bipolar transistors Q
1
, Q
2
forming the current switch S
1
, one having a higher base voltage is turned ON, and emitter potentials of Q
1
, Q
2
represent values lower by corresponding base-emitter voltages V
BE
than the higher base potential.
The differential ECL circuit operates as explained below.
One of the resistors R
1
, R
2
connected to one of the npn bipolar transistors Q
1
, Q
2
currently in its ON state permits a current I to flow from a reference voltage point for giving the reference potential GND to one end, and the potential of its other end decreases to −R
X
I. Further, in the emitter follower, a potential −R
X
I−V
BE
which is lower than the potential −R
X
I by the base-emitter voltage V
BE
of the ON-state npn bipolar transistor Q
3
or Q
4
is taken out from the output terminal as an output signal OUT or /OUT of a LOW level. On the other hand, the other of the resistors R
1
, R
2
connected to OFF-state one of the npn bipolar transistors Q
1
, Q
2
does not introduce the current from the reference potential point for giving the reference potential GND to one end, and maintains a potential substantially equal to the reference potential GND at the other end. Therefore, in the emitter follower, a potential GND−V
BE
lower than the reference potential GND by the base-emitter voltage V
BE
of the ON-state npn bipolar transistor Q
3
or Q
4
is taken out from the output terminal as an output signal OUT or /OUT of a HIGH level.
As a result, when, for example, the base potential of the npn bipolar transistor Q
1
is −0.9 V and the base potential of Q
2
is −1.7 V, the npn bipolar transistor Q
1
is turned ON, and emitter potentials of Q
1
, Q
2
become −0.9 V−V
BE
=−1.8 V.
In the above-explained differential ECL circuit, however, when the base potential of the npn bipolar transistor Q
1
is switched from −0.9 V to −1.7 V, and the base potential of Q
2
from −1.7 V to −0.9, the base potential of Q
1
and the base potential of Q
2
transitionally becomes equal, and the emitter potentials of Q
1
and Q
2
decrease to −1.3 V−V
BE
=−2.2 V, which causes the following problem. If the power source potential V
EE
is higher than −2.2 V, then no current flows in the current switch S
1
for a while, where two outputs OUT and /OUT, which must be differential, both remain in the HIGH level. Therefore, the conventional differential ECL circuit cannot ensure stable operations unless the power source potential V
EE
is lower than −2.2 V, and therefore needs an additional power source for generating the power source potential V
EE
in addition to the power source for generating the a terminal voltage V
TT
(=−2 V).
As reviewed above, there is a difficulty in maintaining stable operations required as a stable logic circuit by applying a typical ECL-level signal to a differential ECL circuit and by using a low voltage power source of approximately −2 V to activate the circuit. Not only for differential ECL circuit, the above discussion essentially applies also to single-end ECL circuits in which only structural difference lies in fixing one of input signals to a predetermined potential (typically, −1.3 V).
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a semiconductor integrated circuit, namely an ECL circuit, which can be operated in a stable mode even by a low voltage power source of approximately −2 V.
According to the invention, there is provided a semiconductor integrated circuit comprising an additional circuit for generating a differential input signal of a potential within a predetermined range in response to an input signal; and an ECL circuit to which the differential input signal is introduced. Since the circuit for shifting the potential level of the input signal toward higher potentials is added to a conventional differential ECL circuit so as to shift the levels of emitter potentials of npn bipolar transistors forming a current switch toward higher potentials, an improved ECL circuit can be realized, which can ensure a continuous flow of a current and can maintain stable operations even in an instant where base potentials of the npn bipolar transistors are switched by a standard ECL-level signal even when the power source voltage is around −2 V.
A second aspect of the invention is configured to introduce a second reference potential V
REF
, in lieu of an input signal V
/IN
′, to bases of the npn bipolar transistors forming the current switch, but it is essentially based on the same theory as that of the first aspect. Therefore, also the semiconductor integrated circuit according to the second aspect can realize an ECL circuit capable of maintaining stable operations.


REFERENCES:
patent: 4359653 (1982-11-01), Takamasa
patent: 4970417 (1990-11-01), Kubota
patent: 5045807 (1991-09-01), Ishihara et al.
patent: 5072136 (1991-12-01), Naghshineh
patent: 5107145 (1992-04-01), Kurashima
patent: 5610539 (1997-03-01), Blauschild et al.
patent: 4-88716 (1992-03-01), None
Taub et al. Digital Integrated Electronics. McGraw-Hill, pp. 229-230, 1977.

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