Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1999-07-12
2001-05-08
Phan, Trong (Department: 2818)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S095000
Reexamination Certificate
active
06229340
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit, more in particular to a basic circuit of a semiconductor integrated circuit constituting a memory LSI or a logic LSI.
(b) Description of the Related Art
A basic logic element having a small input capacitance has been proposed as a basic circuit of a semiconductor integrated circuit. Such a basic logic element is described, for example, in a report entitled “Current-Voltage Characteristics of Small Size MOS Transistors” by B. Hoeneisen appearing in “IEEE Trans. Electron Devices”, vol.19, p108-113 published from IEEE in 1972.
FIG.1
shows a domino circuit including the above mentioned basic logic elements. Numerals
504
and
500
denote a power supply line and a ground line, respectively. The source of a p-channel MOS transistor
105
is connected to the power supply line
504
, and the drain thereof is connected to an input of an output inverter
200
. The source of an n-channel MOS transistor
101
is connected to the ground line
500
. Between the drain of the p-channel MOS transistor
105
and the drain of the n-channel MOS transistor
101
are connected in parallel an n-channel MOS transistor
104
and a serial circuit including n-channel transistors
102
and
103
. A numeral
400
denotes a clock signal which is input to the respective gates of the p-channel MOS transistor
105
and of the n-channel MOS transistor
101
. Numerals
301
to
303
denote input signals which are input to the gates of the n-channel MOS transistors
104
,
103
and
102
, respectively. An output signal
304
of the inverter
200
constitutes the output signal of the domino circuit.
When the clock signal
400
falls to a low level, the p-channel MOS transistor
105
turns ON to raise a node
503
to a high level to conduct a pre-charging, and the output signal
403
falls to a low level from the inverter
200
. When the clock signal
400
rises to a high H level, the output signal
403
from the inverter
200
falls to a high level because the p-channel MOS transistor
105
turns OFF and the n-channel MOS transistor
101
turns ON. The both of the input signals
303
and
302
are at a high level, or the input signal
301
is at a high level to make the potential of the node
503
to a low level. The potential of the node
503
remains unchanged and the output signal
304
remains at a low level unless both of the input signals
303
and
302
rise to a high level, and the input signal
301
rises to a high level even if the input signal
300
rises to a high H level. In other words, this domino circuit is a logic circuit for providing an OR between data
301
and an AND of data
302
and data
303
. The respective n-channel MOS transistors
101
to
104
are designed to have the same threshold values.
In the semiconductor integrated circuit, the elevation of the operation speed and the reduction of power consumption are always required.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention, in view of the above, to provide a basic circuit employable in the above domino circuit in which elevation of its operation speed, extension of a retention time by means of reduction of a leakage current and reduction of power consumption can be attained.
The present invention provides a semiconductor integrated circuit comprising: a first transistor of a first conductivity-type having a source connected to a first source line and a drain; a second transistor of a second conductivity-type having a source connected to a second source line and a drain; and a plurality of third transistors of said second conductivity-type connected in series between the drain of said first transistor and the drain of said second transistor, each of said third transistors having a gate for receiving an input signal, said second transistor and at least one and not all of said third transistors having a threshold voltage lower than a threshold voltage of the others of said third transistors.
In accordance with the present invention, the high speed operation of the circuit, the extension of the signal retention time secured by the reduction of a leakage current and the decrease of the power consumption can be realized by serially inserting the transistors having the different threshold values between the first power source line and the second power source line.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.
REFERENCES:
patent: 5208489 (1993-05-01), Houston
patent: 5532625 (1996-07-01), Rajivan
patent: 5677641 (1997-10-01), Nishio et al.
patent: 6104212 (2000-08-01), Curran
patent: 2-98213 (1990-04-01), None
patent: 5-268065 (1993-10-01), None
patent: 6-29834 (1994-02-01), None
patent: 10-56373 (1998-02-01), None
B. Hoeneisen et al., “Current-Voltage Characteristics of Small Size MOS Transistors”, Mar. 1972, IEEE Transactions on Electron Devices, pp. 382-383.
NEC Corporation
Phan Trong
Young & Thompson
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