Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1999-04-28

2001-03-13

Nguyen, Matthew (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

Reexamination Certificate

active

06201378

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor integrated circuit, including a dynamic random access memory (generally abbreviated “DRAM”) and having an ability to stably produce an intended output voltage.
Normally, in a semiconductor integrated circuit including a DRAM, a plurality of word lines and a plurality of pairs of bit lines crossing the word lines are arranged in the form of a matrix. A plurality of memory cells are formed at intersections between the word lines and bit lines. The memory cells constitute a memory cell array.
Assume that data of “1” or “0” is read from a memory cell selected from among the plurality of memory cells. The potential at a pair of bit lines to which the memory cell is connected is varied according to electric charges accumulated in a cell capacitor in the memory cell. The variation in the potential at the bit lines is detected by a sense amplifier. The variation in the potential at the bit lines must be detected reliably by using a current that is as small as possible (i.e., with minimum power consumption). A method normally adopted for this purpose will be described below. That is to say, before the electric charges which have been accumulated in the cell capacitor in the memory cell are redistributed on the pair of bit lines according to the capacitance offered by the bit lines, the bit lines are short-circuited. The bit lines are then precharged so that the potential at the bit lines will be equal to a certain supply voltage (for example, a half of a high-level supply voltage Vcc (=Vcc/2)).
On the other hand, a high-level supply voltage Vcc or a low-level supply voltage Vss (=0 V) is applied to a cell storage node of the capacitor in the memory cell. At this time, either the high-level supply voltage or the low-level supply voltage is applied depending on whether or not the memory cell has been selected. In a typical DRAM, the capacitance of a cell capacitor is required to be as large as possible in order to make the data holding time relatively long. For this purpose, it is necessary to reduce the thickness of an insulating film of the cell capacitor as much as possible. As the thickness of the insulating film decreases, the durability of the insulation of the cell capacitor, when a high voltage is applied to the cell capacitor, deteriorates. The potential at an electrode (cell plate node) opposed to the cell storage node of the cell capacitor is therefore set to Vcc/2. Thus, even when the supply voltage Vcc or Vss is applied to the cell storage node of the cell capacitor, a potential difference between both surfaces of the insulating film of the cell capacitor is merely Vcc/2. More specifically, in the case in which the potential at the electrode opposed to the cell storage node of the cell capacitor is set to Vcc/2, a voltage applied to the insulating film is only a half of a voltage applied thereto when the potential at the electrode opposed to the cell storage node of the cell capacitor is set to Vcc or Vss. Consequently, the capacitance of the cell capacitor can be made relatively large by reducing the thickness of the insulating film. This is advantageous in elongating the data holding time.
In recent years, especially, a DRAM has been required to operate with a supply voltage that is as low as possible, for example, a supply voltage (Vcc) which is equal to or less than 2 V. This is intended to minimize power consumption of the whole semiconductor integrated circuit. As mentioned above, in a typical DRAM, a voltage used to precharge the bit lines or the potential at an electrode opposed to a cell storage node of a cell capacitor is usually set to Vcc/2. Therefore, it is necessary to stably generate a relatively low voltage which is equal to or less than 1 V.
Now, referring to
FIGS. 1
to
5
that will be mentioned later in “BRIEF DESCRIPTION OF THE DRAWINGS,” an exemplary configuration of a bit line precharging circuit in a typical DRAM, and an exemplary structure of a memory cell, will be described below. A variation in the potential at bit lines occurring when the bit lines are precharged, and an exemplary configuration of a semiconductor integrated circuit having a conventional constant voltage generating circuit will also be described. The above description is intended to reveal the reasons why it is necessary to generate a voltage that is a half of a supply voltage Vcc (that is, Vcc/2) in the DRAM. Also, the above description is intended to clarify problems underlying the generation of the voltage Vcc/2 that is equal to or less than 1 V.
In
FIG. 1
, an outline configuration of a typical DRAM is shown.
As shown in
FIG. 1
, the typical DRAM has a memory cell array
100
in which a plurality of word lines and a plurality of pairs of bit lines are arranged in the form of a matrix. Moreover, a plurality of memory cells is formed at intersections between the word lines and bit lines. Furthermore, the DRAM includes a decoder
600
for decoding control address bits A
0
to Am (where m is any positive integer equal to or larger than 1) that are inputted via an input buffer
500
. The decoder
600
then produces a memory cell selection signal which is used to select a specific memory cell. The decoder
600
applies a certain boosted voltage Vpp (a voltage higher than a supply voltage Vcc that is an internal voltage) to a word line to which the specific memory cell is connected, and thus selects the word line. Output data is sensed or data is rewritten, whereby data is read from the specific memory cell or written into the specific memory cell.
Furthermore, the DRAM includes a sense amplifier
200
. For reading a specific memory cell selected by the decoder
600
, the sense amplifier
200
detects electric charges transferred from the cell capacitor Cc (See
FIG. 3
that will be described later) in the specific memory cell. The sense amplifier
200
thus reads data from the memory cell. The data which has been read by the sense amplifier
200
is amplified up to a given level by a main amplifier
300
. The resultant data is then outputted as digital I/O data of bits DQ
0
to DQn (n=0, 1, 2, —) to the outside of the DRAM.
In the above-mentioned DRAM, it is the bit line pre-charging circuit and cell capacitor that require the voltage Vcc/2 that is half of the supply voltage Vcc (output voltage Vpr in FIGS.
2
and
3
). Herein, the bit line precharging circuit is included in the sense amplifier
200
shown in FIG.
2
. The cell capacitor is included in any memory cell
100
shown in FIG.
3
. In
FIG. 1
, the sense amplifier
200
and memory cell
100
are hatched in an effort to explicitly show the components that use the voltage equivalent to half of the supply voltage Vcc.
To be more specific, the bit line precharging circuit in the sense amplifier
200
shown in
FIG. 1
includes bit line precharging transistors
210
,
220
and
230
which precharge a pair of bit lines BL and /BL to select the specific memory cell. One of the memory cell selection transistors (
230
) is realized by an NMOS transistor (n-channel MOS transistor) and has a source and a drain (or a drain and a source) thereof connected to the pair of bit lines BL and /BL, respectively, so as to equalize potentials at both of the pair of bit lines BL and /BL memory cell, and inputs a precharge enabling signal &phgr; through a gate thereof. The other two bit line precharging transistors (
210
and
220
) are realized by two NMOS transistors for precharging the pair of bit lines BL and /BL. In this configuration, a drain (or source) of the bit line precharging transistor
210
is connected on one bit line BL. A drain (or source) of the other bit line precharging transistor
220
is connected to the other bit line /BL. Further, the sources (or drains) of the bit line precharging transistors
210
and
220
are connected to a common node. A precharging output voltage Vpr (for example, a half of a supply voltage Vcc (Vcc/2)) is applied to the common node. The precharge enabling signal &phgr; is app

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