Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2003-04-09
2004-06-08
Nguyen, Minh (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06748571
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35USC §119 to Japanese patent application No. 2000-089372, filed on Mar. 28, 2000, the contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor inspecting system, a semiconductor defect analyzing system, a semiconductor design data modifying system, a semiconductor inspecting method, a semiconductor defect analyzing method, a semiconductor design data modifying system, and a computer readable recorded medium. More specifically, the invention relates to the quantitative analysis of defects, which are generated in a semiconductor device in accordance with the characteristics of the design of the device, the analysis of the cause of the defects, which is carried out on the basis of the quantitative analysis, and the modification of the design using these analyses.
2. Description of the Prior Art
In a conventional inspection in semiconductor devices, particularly in an inspection in an irregular or random pattern, there is used a method for comparing the pattern of a chip C
2
, which is an object to be inspected, with the pattern of another chip Cl among chips in a semiconductor substrate S to detect the difference there between as a defect DF, as shown in, e.g., the schematic diagram of FIG.
1
. According to this detection method, it is required to carry out the inspection for a long time when the area of an inspection region is extended in accordance with the extension of the area of the chip or when the detection sensitivity is raised in order to detect finer defects. In order to shorten the inspection time, there is carried out a so-called random sampling for choosing a region, which is to be inspected in a chip, and a chip, which is to be inspected, at random.
However, when the random sampling is carried out, the true number of defects can not be grasped if the positions of defects are biased, so that there is a problem in that erroneous results are obtained when the total number of defects is quantified.
There are also relatively similar patterns among random patterns. If the random sampling is carried out with respect to such patterns, similar patterns are duplicated to be chosen. For that reason, when defects caused by the characteristics of the patterns are intended to be detected, the inspection efficiency is not only bad, but a pattern to be inspected is also not chosen as an object to be inspected, so that some defects are overlooked.
On the other hand, conventionally, when the cause of defects is intended to be analyzed, detected defects are observed by an electron microscope or the like, and the cause of the defects is guessed. However, it can not be clarified how such defects are caused, particularly, what characteristics of patterns or processes, what variation and what probability the defects are generated, or how these causes are combined to generate the defects, and what range of design characteristics and variation in processes cause the defects.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor inspecting system, semiconductor inspecting method and computer readable recorded medium for precisely and efficiently qualifying and outputting defects which are generated in a pattern in accordance with the characteristics of a design.
It is another object of the present invention to provide a semiconductor defect analyzing system, semiconductor defect analyzing method and computer readable recorded medium for analyzing the cause of defects, which are generated in a pattern, in connection with information on a design characteristic and a process result.
It is a further object of the present invention to provide a semiconductor data modifying system, semiconductor data modifying method and computer readable recorded medium capable of utilizing the result of the analysis of defects to modify the design of a pattern in a design stage before a semiconductor process so that the possibility of generating defects is lower.
According to a first aspect of the present invention, there is provided a semiconductor inspecting system comprising: a first memory for storing therein a design data of a semiconductor device; a data retrieving part for extracting an inspected-object region from the first memory, the inspected object region being a region serving as an object to be inspected; a design characteristic item data preparing part for deriving numerical values indicative of design characteristics of the design data every one of lattice regions which are obtained by dividing the inspected object region extracted by the data retrieving part into lattices of an optional size and for preparing a design characteristic item data; a characteristic classification preparing part for classifying the design characteristic item data into a desired number of groups to prepare a characteristic classification data; a sampling part extracting the lattice regions at random from the characteristic classification data at a certain sampling rate with respect to the number of the lattice regions belonging to the groups; a second memory for storing therein a defect inspection data which is a data concerning a defect obtained by inspection with respect to a pattern of the lattice regions extracted at the sampling rate from processed patterns which are processed on the basis of the design data; and an operation part for calculating the number of defects in the whole inspected object region on the basis of the defect inspection data, the character classification data and the sampling rate.
According to the first aspect of the semiconductor inspecting system according to the present invention, the design characteristic item data preparing part derives a numerical number indicative of the design characteristic of the design data and prepares the design characteristic item data, and the characteristic classification data preparing part classifies the design characteristic item data into the desired number of groups to prepare the characteristic classification data. Moreover, the operation part calculates the number of defects in the whole inspected object region on the basis of the defect inspection data, the character classification data and the sampling rate. Therefore, it is possible to more accurately quantify defects caused by a design of a semiconductor device.
It is advantageous in the semiconductor inspecting system that the defect inspection data include a data on the degree of defects and the operation part outputs the sum total of defects every degree of defects.
The defect inspection data may be a data obtained by comparing an ideal shape data, which is a simulation result based on the design data, with a shape data of the defects in the processed pattern.
The characteristic classification data preparing part may classify the design characteristic item data using a neural network.
According to a second aspect of the invention, there is provided a semiconductor defect analyzing system comprising: a first memory for storing therein a design data of a semiconductor device; a data retrieving part for extracting an inspected object region from the first memory, the inspected object region being a region serving as an object to be inspected; a second memory for storing therein a defect inspection data concerning an actual defect and a degree of the defect which are obtained by inspecting a processed pattern which is processed on the basis of the design data; a design data processing part for acquiring a first lattice region by dividing the inspected object region by a lattice having an optional size on the defect inspection data so that a place at which the defect has occurred is arranged at the center thereof, the optional size being given as a parameter, and for acquiring a second lattice region by dividing the inspected object region by the lattice on the basis of the defect inspection data so that a n
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