Semiconductor input/output circuit arrangement

Details Semiconductor input/output circuit arrangement Semiconductor input/output circuit arrangement

2002-08-26

2004-10-19

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S226000

Reexamination Certificate

active

06807078

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor input/output arrangement, and particularly to an arrangement for reducing the semiconductor area set aside for input and output.
2. Description of the Related Art
Semiconductor circuits comprise an area of silicon onto which different circuit components are formed by doping with various chemical constituents. Such doping forms multiple devices such as latches and transistors to create memory and processing circuitry as is well known to those skilled in the art. To connect exterior components to the circuit, pins, balls or other connections are provided which connect to pads which in turn connect to the semiconductor circuit via input/output circuitry. Such arrangements are known. The problem with such arrangements, however, is the ever increasing requirement for millions of components to be constructed on a given circuit. This results in increased area of silicon used and greater cost. We have appreciated the need to minimize the area of a semiconductor circuit required for input/output connection.
Semiconductor circuit design typically uses a “library” approach in which divisible parts of circuits are designed and implemented in repeating arrangements. The divisible parts are referred to as library cells. We have further appreciated that circuit design using libraries should use area efficiently for input/output connection.
BRIEF SUMMARY OF THE INVENTION
In a broad aspect, the invention provides a semiconductor circuit arrangement and design methodology in which active circuitry, input/output circuitry and input/output pads are provided, and the protection circuitry is provided as library cells at a reduced frequency than usual.
In particular, there is provided a method of producing a semiconductor circuit with an area saving in comparison with a conventional circuit using library cells, the circuit having active circuitry, an input/output interface comprising separate IO cells and pads for external connection to the active circuitry via the IO cells, comprising:
determining the ratio of power/ground pads to input/output pads for the interface in the conventional circuit;
determining the width of each IO cell of the conventional circuit;
producing IO cells of a width substantially equal to the width of each IO cell of the conventional circuit multiplied by a factor based on the ratio of power/ground pads to input/output pads, but of corresponding reduced height; and
producing power/ground pads and input/output pads for connection to the IO cells grouped together in the ratio determined for the conventional circuit.
The invention is defined in the claims to which reference is now directed.


REFERENCES:
patent: 5365091 (1994-11-01), Yamagishi
patent: 5548135 (1996-08-01), Avery
patent: 5760428 (1998-06-01), Colwell et al.
patent: 5777354 (1998-07-01), Cheung et al.
patent: 5889713 (1999-03-01), Chan et al.
patent: 5943254 (1999-08-01), Bakeman et al.
patent: 6078068 (2000-06-01), Tamura
patent: 6078514 (2000-06-01), Takemae et al.
patent: 6130484 (2000-10-01), Kameda et al.
patent: 6362497 (2002-03-01), Hiraga
patent: 0 563 973 (1993-10-01), None
patent: 0 660 410 (1995-06-01), None
Mack, W. et al., “New ESD Protection Schemes for BiCMOS Processes with Application to Cellular Radio Designs,” inProceedings of the International Symposium on Circuits and Systems, IEEE, vol. 4, conf. 25, San Diego, May 10-13, 1992, pp. 2699-2702.

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