Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-06-03
2001-10-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S230060, C365S189040
Reexamination Certificate
active
06310803
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly to a semiconductor memory device including a plurality of memory blocks.
2. Description of the Background Art
In semiconductor memory devices, a defective memory cell is replaced by a spare memory cell to equivalently repair the defective memory cell and to improve the yield of products. The flexible redundancy method has been proposed as one of redundant circuit structures in which a spare memory cell for replacing and repairing such a defective memory cell is provided.
One example of conventional semiconductor memory devices having the flexible redundancy structure will be described briefly with reference to FIG.
49
. The conventional semiconductor memory device shown in
FIG. 49
includes sense amplifier blocks MX
1
, MX
2
, MX
3
, . . . MXn. The sense amplifier blocks shown in
FIG. 49
are formed of a plurality of memory cells corresponding to one sense amplifier column. Sense amplifier block MX
1
includes a spare row SR
1
(may include a plurality of spare rows). By using spare row SR
1
in sense amplifier block MX
1
, it is possible to replace and repair a memory cell in another block (sense amplifier block MX
3
, for example).
In the conventional semiconductor memory devices, operation of row circuitry is carried out after determination as to whether replacing and repairing using a spare memory cell is to be performed. Accordingly, access time is delayed because of the time necessary to determine spare replacement.
In order to prevent this problem, a memory block including a normal memory cell and a memory block including a spare memory cell are simultaneously selected and activated and, thereafter, data is finally written to or read from either of the memory blocks. However, this method increases power consumption, contrarily to the demand for reducing power consumption.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor memory device capable of reducing power consumption and operating at high speed.
A semiconductor memory device according to one aspect of the present invention includes: a plurality of normal blocks including a plurality of normal memory cells; a spare block including a plurality of spare memory cells for replacing and repairing a defective normal memory cell in a normal block in a prescribed correspondence therewith; a selecting circuit responsive to an external address signal for selecting a corresponding normal block and a corresponding spare block; a spare determining circuit responsive to an external address signal for determining whether or not to carry out replacing and repairing using the spare block; a plurality of sense amplifier blocks, the plurality of sense amplifier blocks being arranged corresponding to the plurality of normal blocks and the spare block and each operating to read/wlite data from/to a corresponding normal block or a corresponding spare block; a plurality of selection gates, the plurality of selection gates being arranged corresponding to the plurality of normal blocks and the spare block and each coupling a corresponding normal block or a corresponding spare block to a corresponding sense amplifier block; a selection gate controlling circuit for controlling opening and closing of the plurality of selection gates to simultaneously couple the selected normal block to the corresponding sense amplifier block and the selected spare block to the corresponding sense amplifier block prior to the determination result of the spare determining circuit; and a controlling circuit for carrying out data reading/writing operations on the selected normal block or the selected spare block according to the determination result of the spare determining circuit.
Accordingly, a major advantage in the above described aspect of the present invention is that a high speed operation can be realized by coupling a normal block and a spare block to a corresponding sense amplifier block prior to determination of spare replacement.
Especially in a refresh mode, the level of gate control signals is controlled according to the determination result of spare replacement. As a result, power consumption can be reduced in the refresh mode.
Especially in the alternately arranged shared sense amplifier structure, a high speed operation is made possible.
Especially when the spare block and the normal block belong to different mats, a high speed operation is guaranteed.
A semiconductor memory device according to another aspect of the present invention includes: a plurality of normal blocks including a plurality of normal memory cells; a spare block including a plurality of spare memory cells for replacing and repairing a defective normal memory cell in a normal block in a prescribed correspondence therewith; a selecting circuit responsive to an external address signal for selecting a corresponding normal block and a corresponding spare block; a spare determining circuit responsive to an external address signal for determining whether or not to carry out replacing and repairing using the spare block; a plurality of sense amplifier blocks, the plurality of sense amplifier blocks being arranged corresponding to the plurality of normal blocks and the spare block and each operating to read/write data from/to a corresponding normal block or a corresponding spare block; a plurality of selection gates, the plurality of selection gates being arranged corresponding to the plurality of normal blocks and the spare block and each coupling a corresponding normal block or a corresponding spare block to a corresponding sense amplifier block by opening and closing themselves according to gate control signals; and a selection gate controlling circuit for setting a plurality of gate control signals at a coupling level, an intermediate level or a non-coupling level, the selection gate controlling circuit setting the plurality of gate control signals from the intermediate level to the coupling level or from the intermediate level to the non-coupling level according to the determination result of the spare determining circuit.
Accordingly, a major advantage in the above described aspect of the present invention is that a high speed operation is guaranteed and power consumption can be reduced by controlling the level of the gate control signals at three stages and setting the level according to the determination of spare replacement.
Especially in the alternately arranged shared sense amplifier structure, a high speed operation and power consumption reduction are made possible.
Especially in the refresh mode, spare replacement in the next refresh cycle is predetermined according to a count value. Thus, the refresh operation can be performed at timing similar to that of the normal mode without delaying the timing of an internal operation.
Especially in the refresh mode, spare replacement in the next refresh cycle is predetermined according to a count value. If the determination of spare replacement is the same between successive refresh cycles, the state of the gate control signals is maintained. Thus, the refresh operation can be performed at timing similar to that of the normal mode without delaying the timing of an internal operation. Further, power consumption associated with the selection gate controlling circuit can be reduced.
Especially when the spare block and the normal block belong to different mats, low power consumption in the refresh mode and a high speed operation in the normal mode are guaranteed.
Especially, the gate control signals are set at the intermediate level (Vcc) between the coupling level (Vpp) and the non-coupling level (GND) in the standby state. Thus, power consumption associated with the selection gate controlling circuit can be reduced.
Especially, the timing for coupling level setting and the timing for non-coupling level setting are adjusted. Even if a fall of the gate control signals is delayed, a large time margin and a higher access time speed are allowed.
A se
Le Thong
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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