Semiconductor floating gate memory cell

Static information storage and retrieval – Read/write circuit – Bad bit

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365185, G11C 1140

Patent

active

045802475

ABSTRACT:
A semiconductor memory cell includes a source-drain series connection of several memory transistors each comprising electrically floating gates and being of the depletion type, with a selection transistor being disposed between a first bit line and a second bit line. The memory cell remains programmable as long as one of the series-arranged memory transistors has an injector oxide free from defects. The memory transistors having an injector oxide damaged by a breakdown are not programmable but do not affect the programmability of the respective semiconductor memory cell.

REFERENCES:
patent: 4514830 (1985-04-01), Hagiwara et al.

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