Semiconductor fin integration using a sacrificial fin

Details Semiconductor fin integration using a sacrificial fin Semiconductor fin integration using a sacrificial fin

2007-02-23

2010-12-14

Garber, Charles D (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S151000, C438S157000, C257SE21409

Reexamination Certificate

active

07851340

ABSTRACT:
There is a method for forming a semiconductor device. Portions of a sacrificial layer are removed to expose a first seed layer region. The first seed layer region corresponds to a first semiconductor region, and a remaining portion of the sacrificial layer corresponds to a second semiconductor region. An epitaxial semiconductor material is deposited over the first seed layer region. A capping layer is formed to overlie the epitaxial semiconductor material and the remaining portion of the sacrificial layer. Portions of the capping layer are removed to form a capping structure that overlies a part of the remaining portion of the sacrificial layer. Portions of the sacrificial layer not covered by the capping structure are removed to form a sacrificial structure having sidewalls. Fin structures are formed adjoining the sidewalls by depositing a semiconductor material along the sidewalls. Portions of the capping structure are removed to expose portions of sacrificial layer between adjacent fin structures. Portions of the sacrificial material between the adjacent fin structures are removed.

REFERENCES:
patent: 6222259 (2001-04-01), Park et al.
patent: 2005/0048727 (2005-03-01), Maszara et al.
patent: 2005/0087811 (2005-04-01), Liao et al.

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